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Below is a minimalistic schematic of a folded cascode op-amp input stage. The node Bias is usually drawn like a fixed voltage, which consequently makes the drain voltage of the input transistors also fixed.

schematic

simulate this circuit – Schematic created using CircuitLab

My question is: Why doesn't one take the Bias from the input transistors' common source like below? That would have the advantage of having the drain voltage of the input transistors elegantly track the input voltage, keeping the transistors in a constant state floating on the input voltage. This would nullify input capacitance to some extent. Also, one could omit any bias generation circuitry.

schematic

simulate this circuit

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  • \$\begingroup\$ Does this not reduce the input stage ac gain to unity? \$\endgroup\$
    – RussellH
    Commented Apr 25, 2023 at 17:27
  • \$\begingroup\$ @RussellH I had such intuition, too, initially, but the gain is no different from a cascode with fixed bias, and that makes sense: The actual (fixed) cascode bias voltage doesn't influence the stage gain, so one can choose it deliberately or might as well dynamically adjust it on the fly. \$\endgroup\$
    – tobalt
    Commented Apr 25, 2023 at 17:55

2 Answers 2

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There are a couple of points we need to consider.

  1. A folded cascode topology is generally used to get good input and output common modes. If bias is connected to the tail of the diff pair, the output common mode gets limited by the input common mode particularly when input common mode is low. When input common mode is at it's highest level, there is risk of putting i1, i2 in linear region.

  2. If the input is a GND referred signal, bias will also become GND referred and that will degrade the PSRR of the opamp because bias has to be connected to a supply referred node to get good PSRR.

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  • \$\begingroup\$ Thanks for these points..About 1: in an op-amp, where you have more stages after the input, the output range isn't really a concern. 2: The cascode potential doesn't really affect the voltage gain, so I intuitively doubt the PSRR argument but will have to simulate :) \$\endgroup\$
    – tobalt
    Commented Apr 25, 2023 at 17:09
  • \$\begingroup\$ Point1 was a generic comment. If bias point is ok in your specific case, no issues. Regarding point2, yes, voltage gain may not change but, PSRR (atleast high frequency where the parasitic cap across i1, i2 will lower the impedance across the current source) will worsen if you connect a ground referred node to bias. You may need to introduce a parasitic mismatch to really capture the impact on PSRR. \$\endgroup\$
    – sai
    Commented Apr 25, 2023 at 17:50
  • \$\begingroup\$ thanks for the explanation..I see what you are suggesting and will explore it in more detail \$\endgroup\$
    – tobalt
    Commented Apr 25, 2023 at 17:58
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I never thought of that!

However, the I3 and I4 current sources have their own \$VDS_{SAT}\$ associated with them (or their own compliance voltage) above ground. Therefore, your "bias" point is located at a \$VDS_{SAT}+V_{gs,M1}\$ above ground. The DC operating points required for both do not match by a \$V_{gs,M1}\$ term, because the voltage the sources of your input pair is at \$VDS_{SAT}\$ only.

Now, you can make I5 as a cascode, so you have \$2VDS_{SAT}\$, but then your voltages wouldn't match by a \$V_{th}\$ term, and you still need to generate a bias voltage for the cascode...

This doesn't mean it'll never work, but you'll have some biasing problems there that might get you in trouble.

Voltage drops

The basic reason why this would be frowned upon, criticized, and probably not robust within an IC is for the reasons I exposed above. All 3 current sources (I3-I5) would be implemented as 3 transistors, they need high overdrive in order to be good current sources. If you connect as you do, you're basically saying that \$V_{ds,I5}\$ is eequal to \${V_{ds,I3}+ V_{gs,M1}\$. In an IC, the drain source voltages across transistors will not change by a lot, specially in deep-submicron. One vdsat could be 200mV and another one could be 250mV. There might be larger differences, but no one will rely on those because they change from PVT to PVT corner.

And sometimes it might work, but then you have to look at the margins (the difference between overdrive voltage and vds) of each transistor. If this margin is small, then this is not robust enough as process variations or any other imperfection might drive it out of saturation easily. In 28nm I typically hit for ~100mV-150mV of margin (my supply is typically 0.9V).

If you implement I3 and I5 as resistor, then you have a degree of freedom there to size your output DC voltage such that, when added to the \$V_{gs,M1}\$, you'll have approximately the same voltage at the top of I5. Then, connecting shorting both nodes could work biasing-wise.

When the output current sources are resistors

Finally, I also add what I said in the comments below, the sources of your input stage now have an extra parasitic capacitance connected in series with your I3 and I4. Might generate some parasitic pole and might also hamper your CMRR at high frequencies. As the other answerer wrote, your PSRR from ground to signal might be hampered if you implement those I3-I4 current sources, a current source will ideally keep the outputs stable (provided there's common-mode feedback if using a differential output), while a resistor will not.

EDIT: I don't know if you mean this, but you have a differential output voltage. If that's how you want to design this, you need a common-mode feedback circuit that takes the average of your outputs can control the bottom current sources.

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  • \$\begingroup\$ Let's think of I3 and I4 as passive load currents (e.g. resistors) to make it easy. The out+/- can be either differentially drive the output stage or I3/4 can be a current mirror with a single-ended output. Either way, one the output voltage(s) are nearly constant (and can be close to the negative rail) when part of such an op-amp input stage, so I don't see the output voltage range argument. \$\endgroup\$
    – tobalt
    Commented Apr 25, 2023 at 17:16
  • \$\begingroup\$ I never mentioned output voltage range, all I'm saying is that the bias voltages of the 2 nodes aren't at the same potential to begin with. When you connect this with feedback, there's a risk the cascode or your input stage might go into triode due these biasing disparities. \$\endgroup\$
    – Designalog
    Commented Apr 25, 2023 at 17:20
  • \$\begingroup\$ @tobalt perhaps if you make the top of your tail current have the same compliance voltage as the gate of your cascodes... might work \$\endgroup\$
    – Designalog
    Commented Apr 25, 2023 at 17:35
  • \$\begingroup\$ maybe I should add that I have no problems getting this to work in a sim, biasing it is easy actually. The question is why I would not do it like this all the time and why available opamp schematics seem to prefer circuit 1, despite the second one working easily. \$\endgroup\$
    – tobalt
    Commented Apr 25, 2023 at 17:53
  • \$\begingroup\$ Namely, connecting Bias and the common source node enforced a 1 V_gs,th as V_ds of the input transistors. This is surely enough to keep them in saturation. \$\endgroup\$
    – tobalt
    Commented Apr 25, 2023 at 18:00

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