I'm looking for a good schematic capture checklist to use when reviewing schematics. This is for the usual issues such as check that you don't have similar but different nets (e.g. GND and GROUND) that are separate and style/readability issues (e.g. no 4-way ties). Either your list or a link to an external one would help.
For what it's worth, I'm using DX Designer, so if you have specific checks you run, let me know about that too.
Do all tantalum caps on rails have at least ~20% overhead? No 25V caps on 24V lines?
Are there bypass caps on the power rails of every chip? Even the ones that don't look like chips, like regulators?
Are there filters on every transistor gate/base? Even the ones in processors?
Are there filters on A/D converter pins?
Are there pullups or pulldowns on every pin where it could matter? Look especially for diodes driving processor inputs or transistor gates, or hanging off an input to the board. Also, outputs of comparators.
Is there impedance on every pin feeding directly into a processor from off-board? A transistor? Something to eat noise and keep it from frying your chip?
Do you have test points on all rails and signals of interest? Including at least one debug pin off any processor?
Is there an LED to indicate power to the board? A second LED, processor controlled, for blink codes?
Is there too much cap on any power rail? Switching regulators have a limit on how much cap they can pull up.
Are all op-amps negative feedback, and all comparators positive feedback? (Obviously there are exceptions to this, I just find it a useful basic rule to check in my applications.)
Are all op-amp and comparator power rails connected in the correct polarity?
Are there any capacitors or zeners directly on the output of an op amp? Should be impedance between.
Are all unused op-amps and comparators tied down properly? Tie op-amp outputs to the negative input, and tie the positive input to common. Tie to common all pins on an unused comparator.
Do all optocouplers have resistors and caps in parallel with their diodes, for noise immunity?
Make sure all user accessible power rails are short-circuit protected.
Check symbol pinouts, especially for new symbols and parts with multiple packages.
Review vendors' latest data sheets and errata to see if anything has changed since you downloaded it.
Have the vendor's FAE review the part of the schematic that uses their part(s)
Label all power nets consistently. Makes it easier to find them during the PCB design.
Check for on- and off-page connections, using the tool's DRC.
Check for same net on different pages without on/off page, using DRC.
Avoid strange symbols (e.g. #) that other tools may not handle well.
All upper case.
Show revisions. Show when drawn, whom by.
Think about EMI/EMC/FCC/UL/CE, etc.
Ease of use:
No 4-way ties.
Label all important nets, e.g. clocks, power even if only going between 2 chips. Makes checking if the clock's serial termination resistor is near the clock driver. Also good for high-current signals that aren't the main power rails, e.g. around the FET or inductor in a DC/DC switcher.
Table of contents on an early page; block diagram on an early page.
Show power and ground on schematic symbols.
Show unused gates/resistors from multi-gate/resistor packages.
Show active low pins on symbol; show active low nets consistently.
No extra connection dots where there isn't a connection.
Not larger than B-sized (11x17) or metric equivalent.
Bus common signals.
Connect by name on-page if it makes it more readable. Similarly don't wire power/ground all over the page, use multiple power/ground symbols.