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I've put LMR33630ADDAR voltage regulator into a PCB with this circuit: enter image description here

It's slightly different from the example from datasheet: enter image description here PG isn't connected, CFF capacitor absent and feedback resistors are 10k vs. 2.49k. I see no issues with these difference since resistor divider is the same for expected 5V output and PG pin may be not used according to datasheet:

Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when not used

And the same for CFF capacitor:

In some cases, a feedforward capacitor can be used across R FBT to improve the load transient response or improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used

So, in result the circuit doesn't work - if I supply 12V input, I see 5.6V on BOOT and VCC pins (which is expected) but 0V on SW pin. I have no idea what's wrong. Furthermore, If I supply 5V, the LMR33630 starts heating to the burning point.

Here is also part of the PCB, probably the issue is in placement:

enter image description here

enter image description here

Would appreciate help of experts in this area since it's my first design of voltage regulation circuit

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  • \$\begingroup\$ Do you have a fast oscilloscope, and do you see signs of instability? I'm looking at the datasheet and it has a suggested layout in fig 10.2; you may want to compare yours with theirs to try to get some insight. \$\endgroup\$
    – nanofarad
    Apr 26 at 23:29
  • \$\begingroup\$ @nanofarad unfortunatelly don't have an oscilloscope. My layout differs from that in reference due to PCB limitations, but still I tried to follow the rules. As I understand, bad layout would cause offsets in voltage or similar instability. But in my case it doesn't work at all. If no other reasons will appear, maybe the chip is counterfeit (it's completely assembled by JLCPCB) \$\endgroup\$
    – brigadir
    Apr 26 at 23:46
  • \$\begingroup\$ The only other difference I see - the heat-sink pad in the ref. layout is connected to ground but left not connected to anything in my case \$\endgroup\$
    – brigadir
    Apr 26 at 23:48
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    \$\begingroup\$ I see below you have solved your problem, but keep in mind that your placement is suboptimal. The SW track is very very thin for no reason, and you will loose efficiency there. In case you respin this PCB, swap the L1 and C18 and make the SW track a plane. \$\endgroup\$
    – Vladimir Cravero
    Apr 27 at 7:52
  • \$\begingroup\$ @brigadir The heatsink pad should be connected to a large plane for thermal dissipation; leaving it connected to nothing provides no benefit. \$\endgroup\$
    – Hearth
    Apr 27 at 15:23

1 Answer 1

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The datasheet says that the exposed thermal pad is also analog ground.

enter image description here

The pad in the image appears to be floating.

The images are a bit confusing The top and bottom layers look identical with the parts on the bottom layer. This is unconventional and could lead to mirror image footprints. Note that red is considered the top layer and blue the bottom layer. While parts can be placed on the bottom layer, the footprints msut be placed as mirro image unless the view is inverted.

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    \$\begingroup\$ Good point regarding thermal pad, I'll check it soon. Regarding layers - sorry for misconception. Both images show top layer, the latter one is just 3D render for better visualization. Bottom layer doesn't contain anything useful \$\endgroup\$
    – brigadir
    Apr 27 at 0:05
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    \$\begingroup\$ Thank you RussellH, it was the reason of the issue. After soldering the thermal pad to ground all works perfectly. Unfortunately one chip has gone, it was sacrificed for the sake of learning \$\endgroup\$
    – brigadir
    Apr 27 at 0:32

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