I am trying to simulate the circuit below (from this paper) at the transistor level using a 0.18um, 1.8V process. The circuit serves as an amplifier for recording neural activities, and uses 2 capacitors (C1) to block DC offset and set the gain.
The OTA is implemented as below:
However, C1 also blocks the DC bias voltage that I set in the signal source, and keeps the input common-mode voltage close to zero. This makes the two input PMOS (M1, M2) work in triode region in my case (Vs is about 750mV), and significantly reduces the Gm of the OTA. The voltage gain is even less than 1 in my simulation.
I'm wondering if this is a problem of the OTA. Should the OTA be designed to operate at fairly arbitrary input common-mode voltages?
Also, is there a way to define the input common-mode voltage as I want (around 350mV) if I keep this configuration?
By the way, I just connected VSS to ground and VDD to 1.8V in my simulation, while in that paper they used \$ \pm 2.5V \$ supply. Don't know if this causes the problem.