-1
\$\begingroup\$

We know that two un/signed integers arithmetic operation using special circuit called full-adder to execute arithmetic operation in Arithmetic Logic Unit (ALU).

The full-adder I mean is classical adder that consist with two half-adder cascaded and an OR-GATE. It has Cin, A, B, S, and Cout pin.

How about two float numbers that represented with IEEE754 standard when doing arithmetic operation? Will the operation using full-adder which same like un/signed integer arithmetic operation uses or.. it will using antoher special circuit?

I think it will using another special unit to operate floating number arithmetic operation that ofcourse consisted with another logic gates since it's not compatible with classical full-adder for integer.

Note that, I'm talking about abstract circuit (logic gates/ALU/full-adder) not physical circuit such as transistor, ground, power, etc.

\$\endgroup\$
9
  • \$\begingroup\$ FP addition and subtraction requires some kind of barrel shifter, one that also tracks the number of required shifts, for the mantissa. That's not in the usual integer ALU repertoire. (Fully combinatorial versions have been made in the past -- Bipolar Integrated Technologies, for example.) \$\endgroup\$
    – periblepsis
    Commented May 2, 2023 at 7:04
  • 4
    \$\begingroup\$ What kind of an answer are you looking for, here? As written, a simple "yes" seems to suffice. \$\endgroup\$
    – Tim Williams
    Commented May 2, 2023 at 7:06
  • \$\begingroup\$ @TimWilliams I know how IEEE754 represented and I know what happen when computer doing addition/substraction for integer. But I don't know what happened when two float numbers doing addition/subtraction. For example 2.71 + 3.14, what happened at there? I think computer will decode the operands (2.71 and 3.14) to the IEEE754 format in binary as the first step. \$\endgroup\$
    – Muhammad Ikhwan Perwira
    Commented May 2, 2023 at 7:11
  • \$\begingroup\$ When you say "2.71 + 3.14", do you mean literally this string representation, and how a programming language interprets that as a number? Or do you mean the floating point values (0x402d70a4 and 0x4048f5c3) and the logic function to sum them? \$\endgroup\$
    – Tim Williams
    Commented May 2, 2023 at 7:17
  • \$\begingroup\$ @Muhammad There will be an ASCII parser that parses the number formats. In the process, this parser will generate the FP result either by doing it in still more software (which is easy to do without the use of any FP hardware at all) or by using FP hardware should it also exist. Once the two numbers are converted, the FP ADD (for example), will unpack the mantissa and exponent and sign and hidden bit and perform stuff that is more than most will want to write about here (in general form, anyway, as it would require a chapter or two.) \$\endgroup\$
    – periblepsis
    Commented May 2, 2023 at 7:18

1 Answer 1

Reset to default
3
\$\begingroup\$

Floating point addition requires mantissa alignment before the add, a shift to align the binary points.

In the case of IEEE754 representation, the adder has to handle the fact that the MSB is implied, not present. This can either be done by inserting an MSB of '1' before a normal adder, or using a special adder which acts as if this has been done.

The insertion of an implied MSB does not apply for denormalised numbers of course, signalled by the exponent under-flowing.

This means that a floating point adder to IEEE754 must do something 'special' above using just a full adder, if it is to do what is specified.

How it does that special stuff, whether it's all encoded in a single cycle of hardware, or whether it takes several microcoded steps, is up to the designer of the chip. It's simply a speed/cost tradeoff.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.