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Half-Bridge Motor Driver

This picture describes the current state of my project that I am working on. I am making a half-bridge high-current motor driver (that will eventually evolve into a full-bridge). The motor is represented by the 100u inductor and 0.1ohm resistor connected to node C, and the motor itself is a Vex 775 Pro motor.

Q1 and Q2 form a mosfet push-pull driver, driving mosfet Q3's gate terminal. Q11 and Q12 are in an identical configuration driving mosfet Q4's gate terminal. The catch is that Q4 is a high-side FET. Currently, Q11 and Q12 are in a bootstrap circuit, so they will have sufficient voltage to drive the gate of Q4, but neither push-pull driver may have sufficient voltage to be driven by itself.

The 3.3V Driver on the left-hand side is an ESP32Wroom module. It runs on 3.3V logic, so that is the max I'm going to get out of it.

The ESP32 does not work for a few reasons:

  1. 3.3V does not match the rail voltage of 12V. The lower N-FET is logic level so it has no issue being driven by 3.3V, but when the N-FET(lets say Q2) is being driven at node F, 12-3.3V is 8.7V, so Vgf = 8.7, so the P-FET is also on, which is very problematic, as that causes a massive shoot through. The P-FET never turns off in this config.

  2. The topside requires a floating ground. There's likely some optocoupler shenanigans I could use to get around this but they're not apparent to me right now.

There are a few tactics I know of in order to drive these two push-pull drivers:

  1. Use a gate driver chip
  2. Use a transformer with DC restoring on the secondary.

And here are my rebuttals to both of these:

  1. If I wanted to use a gate-drive chip I would have already. The idea behind not using a gate-drive chip is that I want to make my own driver circuit. I bought a bunch of gate driver chips and constantly blew them up from the large voltage transients of the circuit (there will be a 15V TVS diode from node A to ground in the final circuit now), and it was always annoying to get more, so if I can learn to make my own then I don't have to play victim to market price swings or stock issues.

  2. Transformers are super expensive. Even the small ones can go for multiple dollars apiece (I'm trying to keep everything in the circuit cheap enough to bulk-buy). They would be an amazing option if I could find one that was cheap enough to bulk-buy and stepped 5V up to 10-12V.

There are some great resources out there by TI on how to design gate drivers, but all of the ones listed in the document I found seem to require a gate-drive voltage that is equivalent to VCC. (LINK TO DOC: https://www.ti.com/lit/ml/slua618a/slua618a.pdf?ts=1683206173466&ref_url=https%253A%252F%252Fwww.google.com%252F)

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    \$\begingroup\$ Q1 and Q11 have their D and S swapped, look at their diodes. When their wiring is corrected then their much lower gate voltages will have them turned on all the time. \$\endgroup\$
    – Audioguru
    May 4, 2023 at 22:55
  • \$\begingroup\$ I am confused. Q1 and Q11 are P-Channel FETs so their diodes should be pointing the reverse of an N-channel. Apologies if that wasn't clear. From what I am aware this is the standard configuration of a push-pull driver circuit. If it is not then my bad. \$\endgroup\$
    – theph
    May 4, 2023 at 23:06
  • \$\begingroup\$ @Audioguru: Yes I saw that too, but there is a voltage boost circuit. The boost is not needed with a high-side PMOS connected as you suggest. A high-side NMOS will require the boost. So the questioner has decision to make, \$\endgroup\$
    – RussellH
    May 4, 2023 at 23:07
  • \$\begingroup\$ Whether you use PMOS or NMOS high side drivers, their gates canot be connected together ar D and F. Before asking to interface the 3,3V MCU you need to get the displayed circuitry working first. \$\endgroup\$
    – RussellH
    May 4, 2023 at 23:09
  • \$\begingroup\$ Their gates can, in fact, be connected together. When a High pulse is sent to the gate connection, the N-FET turns on and P-FET turns off (when Vgs = Vds), and when a low pulse is sent, the P-FET turns on and the N-FET turns off. This is the main idea behind push-pull mosfet drive and is how CMOS fets are connected. In my scenario, Vgs =/= Vds, and so I'm trying to find ways around that. \$\endgroup\$
    – theph
    May 4, 2023 at 23:22

4 Answers 4

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I want to make my own driver circuit.

Your own driver circuits will have to be more robust than commercially available gate drivers. You will find this a bit hard to achieve as a novice.

I bought a bunch of gate driver chips and constantly blew them up from the large voltage transients of the circuit

The mosfet circuit has to be fixed before you even consider driving it. There's nothing wrong with gate driver chips - but probably a lot wrong with how the circuit is assembled. Usually such problems result from poor prototype construction/layout.

I suggest buying some pre-made modules that have mosfets and gate drivers on one PCB, and have a look at how they are laid out.

The 1N4007 boost diode is a very poor choice. It should be a much faster diode - UF4003, 1N4148, or a small Schottky diode.

This motor (as listed in its datasheet) has inrush current spikes of 120A

You are the one supplying the motor. You are in full control over whether there are current spikes, and what their amplitude is. What happens is up to your circuit.

Sure, one just hard-connects the motor winding with low impedance supply through a low resistance, there may be 120A current spike. The idea then is not to do that :)

Transformers are super expensive. Even the small ones can go for multiple dollars apiece

It seems you want to build this circuit from bits and pieces bought cheaply on AliExpress or something like that. I suggest not going this route: you'll run into plenty of fake parts, poorly designed modules, etc.

If a couple dollars is too expensive, you can't afford this circuit anyway. And your time isn't free either. Count your design time at, say, $30 per hour, as a figure to start with. When you'll be making the modules en masse and selling them, you - or the business you work for - must recoup the cost of every hour of your work.

Don't judge the costs of a finished custom circuit by the prices of mass-made, mass-copied, zero-effort (nearly) stuff that's sold on AliExpress and so on. The people who designed those things got paid a long ago - now it's only copies, and cutting corners by using lower quality components and less operating margins.


There's a further issue with the claim that you "bought a bunch of gate driver chips": if you want help with that, you have to share schematics and clear pictures of how you put those circuits together. We can't help you if we don't know what you did wrong. The argument that you have to roll your own driver circuit has no support unless we can establish that off the shelf driver chips won't work. And I bet you that's not the case.

See e.g. this answer for hints about layout.

Gate drivers made from discrete components aren't trivial. Here are a few examples for various applications:

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I made an LTspice simulation of your gate driver, which will have 1.2 A shoot-through, and an alternate design which incorporates source followers that eliminate shoot-through at the expense of a high output which is about 1.5 V lower than the 12 V rail.

MOSFET driver with NMOS and PMOS

It might be better to use an NPN/PNP pair as emitter followers with only about 0.7 V to the rails. Actually with a 100 ohm load the output is essentially zero.

schematic

simulate this circuit – Schematic created using CircuitLab

MOSFET Driver NPN and PNP

This is a 1 us pulse with 100 ns rise and fall times, and the output very nearly follows the input. Drive into a MOSFET gate might show some delay.

Here is the output waveform through a 5 ohm resistor into an STP55NF06L MOSFET and a 100 ohm load.

Driver into MOSFET gate

Here is a simulation of a complete level shifter circuit driving an NMOS half-bridge from a 3.3 V 10 kHz PWM signal and a 12 V power supply. It does not incorporate crossover control. This would probably be best implemented with a separate drive for the high and low side MOSFETs.

Level Shifter MOSFET

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  • \$\begingroup\$ Wow this is amazing, thanks! I was aware of a shoot-through issue, however these mosfets (should) have been rated to handle it. The gate resistors were picked with that in mind. That being said, when I tried designing the NPN/PNP push pull driver IRL, I was getting some funky voltage waveforms on my oscilloscope. Do you have any pointers for what kinds of specs I should be aiming for with NPNs and PNP? I'd imagine high current capability is on that list, but high current usually means low Hfe... I have no idea what is important for a push-pull driver. \$\endgroup\$
    – theph
    May 5, 2023 at 5:08
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Your design will use high-side Q4 with PWM to control acceleration current, and the low-side Q3 (which short-circuits the motor) to control braking current. That's probably not what you intended.

During acceleration, you will have to keep Q3 off, and control motor current with PWM for Q4. Once the desired speed is reached, you then continue to PWM Q4 with low duty cycle to maintain that speed. In this mode of operation, where Q3 is never on, Q3 never pulls node C low to recharge C1. Eventually, with C1's charge decaying, Q4 will have insufficient gate voltage to switch fully on.

Q11 and Q1 are upside down, their drains should be connected together, with both body diodes pointing upwards.

Even with that fixed, you now have brief shoot-through of \$\frac{12V}{5\Omega + 5\Omega}=1.2A\$ via Q11 and Q12, which may significantly discharge C1. Ideally there should be a small delay between Q12 switching off, and Q11 switching on.

The output MOSFETs Q3 and Q4 have 10nF of input capacitance. Combined with the driving impedance of 5Ω, you are looking at gate potential rise and fall times around \$5\Omega \times 10nF = 50ns\$.

The gate driver MOSFETs Q1, Q2, Q11 and Q12 also have significant input capacitance, 1nF, ten times lower. To justify their presence, these MOSFETs will require their own gate driver source with impedance at most ten times higher, 50Ω. Much more than that, and they will themselves become the slowest slewing element in the chain, defeating their purpose. While not difficult, whatever level-translation you employ for nodes D and F will have to be quite beefy too, able to source and sink over 200mA.

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  • \$\begingroup\$ Thanks for the great response! I'll look into the Q11 and Q1 thing. Q3 and Q4 were chosen to have 10nF input capacitance, because (before I thought too much about this whole scenario), I had figured out that if you wanted to charge them up with a 20mA source in 500nS (which is my target time), the largest input capacitance I could have is 10nC... for one FET. Totally forgot I'm powering two hah. I am confused by your last paragraph though. You just said their input capacitance was 10nF and then you said it was 1nF, are you talking about something different? Or am I missing something here... \$\endgroup\$
    – theph
    May 5, 2023 at 4:48
  • \$\begingroup\$ @theph I wasn't clear enough sorry. Q3 & Q4 are 10nF, the others, Q1, Q2, Q11 and Q12, are 1nF. 1nF seems quite high for a more "signal" level function, and it pushes up the requirements for driving the gates of Q1, Q2, Q11 and Q12. \$\endgroup\$ May 5, 2023 at 5:56
  • \$\begingroup\$ My apologies, I mixed up capacitance with gate charge again... How silly of me. How does it push up the requirements of driving the gates of Q1,2,11, and 12? Please correct me if I am wrong but the gate charge supplied to (for example Q3) is from Q2 and is sunk to Q1... but that doesnt make Q2 and Q1 harder to drive, does it? It was my understanding that the gates of these capacitors were separate to that of Q3... but if Cds of Q1,2 are in parallel with Cgs, then the capacitors would add and it would be harder to drive... \$\endgroup\$
    – theph
    May 5, 2023 at 6:10
  • \$\begingroup\$ @theph I mean the gate capacitances of Q1,Q2 etc are also hard to drive. Q1, Q2 etc are fine to drive the gates of Q3 & Q4. But whatever you use to drive the gates of Q1,2,11,12 will have to be quite strong too. \$\endgroup\$ May 5, 2023 at 6:40
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EDIT, per @theph's comment: Replace the lower MOSFET with an N-channel MOSFET with a low gate threshold voltage. Then you can power the low side driver at 3.3 V and drive it with a 3.3 V signal.

Add a level shifter (yes, an IC) between the 3.3 V signal and the "D" input, and another one between the 3.3 V signal and the "E" input

I want to make my own driver circuit

What are these special skills that you have that allow you to design a better gate driver circuit than ON Semi or MicroChip? Consider that these companies may have already solved potential problems that you haven't even become aware of. I believe that this is not a case where reinventing the wheel is called for.

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    \$\begingroup\$ 1) The lower FET cannot simply be replaced with a logic level FET. This motor (as listed in its datasheet) has inrush current spikes of 120A and any logic level fet will have an incredibly hard time driving such a load without massive heat dissipation. The lower FET has RDSon in the microOhm region to allow massive current throughput. 2) No need to be snarky, I have lofty goals. I don't need to design a better gate driver than Onsemi or ST, I hate working with 'black boxes'. Plus making a gate driver looks good on a resume. Thanks for the logic shifter idea tho imma have to look at that. \$\endgroup\$
    – theph
    May 4, 2023 at 22:40
  • \$\begingroup\$ @theph. Thank you. I edited my answer accordingly. \$\endgroup\$ May 4, 2023 at 22:45

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