10
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My code:

module adder(a,b,result);
   input wire [9:0] a,b;
   output wire [10:0] result;
   assign result = a + b;
endmodule

My company recently changed policy to escalate the linting rule (W164a and W164b) mismatch of LHS and RHS bit widths from warnings to errors. Now I either have to waive these lines of code to tell the linting software not to freak out, or I have to prepend 1'b0 to both a & b.

What is the right approach here?

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2 Answers 2

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The right approach is to discuss this situation with the people in your company who recently changed the policy. Your Verilog code is very clean, and it is a common way to add numbers together. Prepending 1'b0 to both a & b will result in code that is not commonly seen.

If you can not convince them to change this back to a warning, then you should waive these lines of code.

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  • 1
    \$\begingroup\$ The reason stated for changing this was a lesson learnt in a previous project where they found some issue because they ignored this warning. I didn't discuss exactly what yet, but will do it. Thanks for the reply! \$\endgroup\$ May 5, 2023 at 19:59
  • 3
    \$\begingroup\$ @nebuchadnezzar_II found some issue because they ignored this warning is unexpected. \$\endgroup\$
    – greybeard
    May 6, 2023 at 5:13
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    \$\begingroup\$ The obvious error case is where a or b is a signed quantity with a negative value and the variable is not marked signed. \$\endgroup\$
    – grahamj42
    May 7, 2023 at 7:12
  • \$\begingroup\$ @greybeard, I agree and I'm not able to imagine such a situation. As grahamj42 points out, we do have the datapath switching in certain modes to signed representation. \$\endgroup\$ May 8, 2023 at 19:27
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IMHO, padding 0's should not be an error. Only implicit casting with the potential loss of data should be a warning or error. Consider using SystemVerilog's explicit casting in place of waivers

assign result = 11'(a + b);
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