# Please explain the highlighted part on the working of a D flip-flop [closed]

The section of the textbook Digital Design by Morris M. Mano and Michael D. Ciletti says the following about D flip-flops:

Another construction of an edge-triggered D flip-flop uses three SR latches as shown in Fig. 5.10. Two latches respond to the external D (data) and Clk (clock) inputs. The third latch provides the outputs for the flip-flop. The S and R inputs of the output latch are maintained at the logic-1 level when Clk = 0. This causes the output to remain in its present state. Input D may be equal to 0 or 1. If D = 0 when Clk becomes 1, R changes to 0. This causes the flip-flop to go to the reset state, making Q = 0. If there is a change in the D input while Clk = 1, terminal R remains at 0 because Q is 0."

How is the value at terminal R dependent on the output Q? Is it a logical fault in the explanation? If it isn't, please explain this part of the reasoning.

The description is certainly misleading, and its correctness is debatable. Because $$\R\$$ and $$\Q\$$ go into a NAND gate, if $$\Q = 0\$$ the the output of the NAND is as if $$\Q = 0\$$; that holds $$\Q'\$$ high, so as long as the preceding circuitry is holding $$\S\$$ high, $$\Q\$$ stays at zero.