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I am using a couple of CD4013BC as frequency dividers as per schematic :

enter image description here

I am checking from a data logger that they are losing some cycles, or not dividing the frequency properly from time to time. The unused IC pins are grounded.

Did anyone experience the same and know the possible reasons why flip flops are not accurate in the 24hours run?

Accurate means if I divide a frequency let's say 100 Hz and I obtain another one of 50Hz for example, sometime I notice the output frequency as logged is higher or lower (75Hz or24 Hz resulting in my datalogger as negative or positive spikes.

I am clocking them with a square wave DC 5v 100Hz

Is this a standard behavior?

As requested, I am feeding this frequency from an optocoupler that is taking the square wave from a zero cross circuit. The optocoupler is feed with 5V, a 4N25.

This is the input, and doesn't looks noisy to me at all :

enter image description here

for proving that, I measured the input from the source before it arrives to the IC and I don't have any frequency changes.

@Simonb

here is an example of the output recorded from the datalogger , directly after the optocoupler. Consequently, when the frequency changes of little variations OR there are these glitches, the flip flop seems to amplify them even more , even with delays before counting back correctly

enter image description here

-- EDIT

Looks like I solved partially just adding a capacitor to the AC output at the very initial stage of the circuit.

enter image description here

@SteveSh

enter image description here

enter image description here

EDIT --

Alright, I will post this to further confirm the GLITCHES theory. I am not saying that a ST is not necessary, just that the CAUSE are the GLITCHES, the EFFECT is then reflected on the IC itself from the noise of the modulated AC source.

So I decided to add a monitor and sync it with my datalogger to see it clearer. It's evident from the below images there are some amplitude modulated signals in the AC Power supply, probably coming from the grid or local switches that are creating these alteration. As the clock below are sync with multiple Chrony instances the signal in time corresponds to the perturbations created by AM modulation. Hence the erratic EFFECTS are reaching the IC with relative consequences.

Image 1 source : AC power supply monitored with a spectrum

[![enter image description here][7]][7]

Image 2 : The not yet cleaned by software frequency coming out from the Flip Flop to the datalogger, with full bandwidth scale (note the timings) :

enter image description here

Image 3 : the frequency from the Flip Flop cleaned with a custom software using FBMWA algorithm (same data from figure 1, just cleaned from the Glitches and focused in bandwidth .

Conclusion my side and correct answer remains for glitches cause first.

enter image description here

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    \$\begingroup\$ No it's not standard behaviour at all. Imagine if all our digital clocks and wristwatches did that. \$\endgroup\$
    – Andy aka
    May 11, 2023 at 5:43
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    \$\begingroup\$ A working flip-flop does not 'lose some cycles'. That is the behaviour of a broken flip-flop. OR it might be the behaviour of an noisyly powered, or noisyly clocked, working flip flop. Show in your question how you a powering and clocking the device, what voltage levels, decoupling, clock source and waveform. If it's thrown together on a breadboard, then you have to be very, very careful indeed with circuit hygiene. \$\endgroup\$
    – Neil_UK
    May 11, 2023 at 5:45
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    \$\begingroup\$ @DoubtfulMonk Now add the rest of the info, schematic from clock source through to oscilloscope / data logger. A photograph of the physical setup would be useful as well. What the missing cycles is telling you is that the circuit is not behaving as you expect it to behave. We seasoned engineers have some guesses as to why that might be happening, but there are so many possible causes that without information, it's just guesses. We need to see that entire circuit as it is, not as you hope it is (because it's not as you hope it is!) \$\endgroup\$
    – Neil_UK
    May 11, 2023 at 6:01
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    \$\begingroup\$ @DoubtfulMonk you keep talking about "frequency changes", but that makes no sense in the context of a flipflop divider: what it literally does is just have a rising edge on every 2. rising input edge. (It might make your own life much easier if you try to understand how that works, instead of viewing it as magic "frequency halfer circuitry", which it isn't.) It doesn't care that the input signal is periodic. So, it is either missing or seeing some edges that do not fulfil your expectation. It's impossible to debug this without a schematic, and an observation of your input when that happens. \$\endgroup\$ May 11, 2023 at 6:02
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    \$\begingroup\$ @DoubtfulMonk The 4013, and indeed most flip flops, have propagation, setup and hold timing such that they can be used safely as /2 as you wish to do, so your linked Q/A is not relevant here, which addresses what happens when the clock and D changes are not related. We do indeed know very little of the details of your circuit. The remedy for that is in your hands. \$\endgroup\$
    – Neil_UK
    May 11, 2023 at 7:41

4 Answers 4

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The chances are that the flipflop is responding to very short glitches on your power supply. Modern ICs can respond to clock inputs measured in nanoseconds. A momentary spike on your supply could be enough to trigger an extra clock cycle. You may need to look more carefully at your input circuit to try to filter out such glitches.

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    \$\begingroup\$ I think this can be corrected answer! You see, N% is still good in this forum. I was thinking to add a MOV to the really input source of the AC circuit (I am using a 9v downstep AC/AC transformer . Still have some glitches , I can see them from my datalogger from the output of the optocoupler over time. But not sure the answer of a MOV will be enough to remove them? \$\endgroup\$ May 11, 2023 at 8:25
  • \$\begingroup\$ I have added a graph from the optocoupler , the signal is directly from the 0 cross , but is the same that will clock the flipflop \$\endgroup\$ May 11, 2023 at 8:29
  • \$\begingroup\$ and of course I am using a custom software to remove the glitches and gaps with a Forward - Backward exponential weighted moving average , so it can be corrected easily by software. But I would like to tend to circuit perfection and find a way to reduce these glitches. Thanks for answering btw. \$\endgroup\$ May 11, 2023 at 8:34
  • \$\begingroup\$ As requested, you need to add a schematic of your full circuit. \$\endgroup\$ May 11, 2023 at 16:09
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You have not provided enough information - like a schematic - to be able to answer with more certainty. But, the outputs of the 4N25 opto is not the nice, sharp edge that's indicated on your 'scope trace, because of the time scale used.

enter image description here

Fed with a slowly varying input, the opto's output is going to slowly change from one state to the next. By slowly I mean relative to the edge rate needed by the '4013 flip flop. According to the data sheet, the maximum (slowest) clock rise or fall time is 15 us. I bet you're not getting that kind of speed out of the opto. And when this happens, it is possible for the flip flop to double clock or not clock on the edge.

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  • \$\begingroup\$ added some more picture with different time-scale, where do you see the distortion? \$\endgroup\$ May 11, 2023 at 15:24
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    \$\begingroup\$ This is the correct answer +1 . OP is violating the datasheet limits on clock rise/fall times (15us maximum with a 5V supply, less at higher voltages) vs. what looks more like 5000us and is getting erratic operation as a direct result. A Schmitt trigger or an optoisolator with crisp output rise/fall are possible solutions . \$\endgroup\$ May 11, 2023 at 15:46
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    \$\begingroup\$ @Doubtful Monk - Is the first picture you added - the one with the slow rise time - the output of the opto, which clocks the flip flop? If so, then that's (the slow rise time) a problem that has to be corrected. \$\endgroup\$
    – SteveSh
    May 11, 2023 at 16:23
  • \$\begingroup\$ @SteveSh yes correct. I will try to add a Schmitt trigger after the optocoupler , thanks a lot \$\endgroup\$ May 11, 2023 at 16:28
  • \$\begingroup\$ @SpehroPefhany these can be related effects, I have updated my answer .The cause are the glitches in this specific case. \$\endgroup\$ May 11, 2023 at 16:57
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A flip-flop is never imprecise. Assuming suitable inputs, it does exactly what it’s told so one can assume the results are real. Here, without a Schmitt trigger, the results may well be hard to reproduce. But if a Schmitt gate follows the optocoupler, and “miscounting” still occurs, the pulses are there all right, just very short.

Without a schematic it’s a bit of a time waster, but here are the things needed for it to work:

  1. A Schmitt trigger on the optocoupler output to condition the outputs.

  2. A clean supply - ideally regulated locally.

  3. Decoupling capacitors at each chip.

  4. Bulk decoupling at board level.

  5. A passive filter before the regulator to get rid of high frequency hash (remove it only after it’s shown to work correctly with and without).

  6. A small capacitor across the phototransistor output to shunt common mode spikes that got converted to differential mode.

  7. A supply voltage large enough for a good noise margin. I’d suggest 9V at minimum, 12V ideally.

I have built similar circuits many times and they usually worked on first try, so there must be something fundamental about your implementation that makes it not work. Please add a complete schematic and a picture of the layout/protoboard.

I usually prefer detecting zero crossings with a general purpose comparator with hysteresis added. With hysteresis symmetric around zero, there phase error averages out to zero. It’s possible to have symmetric hysteresis even with a single supply: after all, the output is AC, so with a capacitor we can shift it down to be around zero. The comparator and LED supply can come from a capacitive dropper.

Anothe robust approach is to have two optocouplers to indicate polarity, not zero crossing, and have a S-R debouncer on the output side, following the Schmitt triggers. Assuming identical optocouplers, the net phase error will be very small as well. A double optocoupler is recommended for this for better matching.

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  • \$\begingroup\$ great suggestions, thanks for answering \$\endgroup\$ May 11, 2023 at 15:37
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Fundamentally this is because the DFF can toggle faster than the edge rates coming from the optocoupler. Therefor noise on the optocoupler's output will multiply clock the DFF.

You need to insert a Schmitt trigger (hysteresis circuit) between the optocoupler and the DFF.

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  • \$\begingroup\$ that's a good suggestion and will try for sure ,thanks \$\endgroup\$ May 11, 2023 at 14:12
  • \$\begingroup\$ but basically the trick is to remove glitches, the problem starts from there. With the capacitor coupled at the ac ingress is already way better \$\endgroup\$ May 11, 2023 at 14:13

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