# Impedance considerations

I'm desiging a PCB which uses USB (2.0) and PCIe (2.1).

USB is not that fast, however it's said its impedance might have to be correctly set to around 90Ohm +/- 15%.

Now on the other hand, PCIe's impedance needs to be set to 85Ohm +/- 15%.

Alright, so it pretty much seems (and as far as I remember correctly), trace length is not important from impedance perspective:

This is how my USB data lines are routed currently:

Trace lengths are the same (?), although it's pretty strange how Eagle8 is handling this highlight.

Am I correct in these below points:

1. 10.4mm is the trace lengths of D_N and D_P.
2. Meander can only make trace lengths equal, has nothing to do with impedance.
3. Trace lengths in differential pair needs to be equal (D_N, D_P).
4. Impedance can be calculated with (t, h, w, s, dielectric constant).

What is "s" actually? Is it the space between D_N and D_P?

If so, as you can see, I can't really make long parallel trace on D_N and D_P, both are very short (10.4mm), so how can I calculate "s" in this case?

## PCIe

Eagle routed PET0 diff pair like this:

I don't have any idea where is the offset distance of the differential pair Eagle uses.

However, pasting values into this calculator (assuming s is distance between those diff traces):

Impedance of this trace is 62.8Ohm, well below 85Ohm - 15%.

1. Why Eagle puts these differential lanes that close to each other?
2. Shall I make more space in between these two to approach 85Ohm better?

Like this, increasing space:

## Update

PCIe signals routing currently:

s = 0.1mm
w = 0.3mm
t Cu = 35um
h = 0.8mm
Er = 4.3 (FR4)
**Z0 = 56.4 Ohm**

Create a new class with spacing = 0.2mm, and width = 0.2mm:

s = 0.2mm
w = 0.2mm
t Cu = 35um
h = 0.8mm
Er = 4.3 (FR4)
**Z0 = 76.4 Ohm**

I know it's not that easy to calculate the impedance, but roughly, is this below routing better in terms of impedance matching to 85Ohms?

• That's a pretty ratty route for USB_D_N and USB_D_P. Just eyeballing it I can come up with a better route for those two signals that meets the length matching requirement (which is what seems to have driven the route taken by USB_D_P) and keeps the two traces together for most of the run. May 11, 2023 at 12:13

What is "s" actually? Is it the space between D_N and D_P?

As shown in your last two figures: yes!

** Others **

1. 10.4mm is the trace lengths of D_N and D_P.

Its the D_N length

1. Meander can only make trace lengths equal, has nothing to do with impedance.

Correct. Length matching is not that super critical for USB 2.0. But: Matching it to +/- 5% is good pratice - as long as routing doesn't get complicated then.

Also: Place a via GND-Vias close to your USB-Vias. They need to be connected to a solid GND plane if possible (on one side is enough!). This helps the fields propagate.

1. Trace lengths in differential pair needs to be equal (D_N, D_P).

See (2.)

1. Impedance can be calculated with (t, h, w, s, dielectric constant)

As show in your last two figures: yes. But the term "approximated" is better suited! The tool you are showing - for sure - is not a high-end field-solver.

1. Why Eagle puts these differential lanes that close to each other?

I guess this depends on ome other settings within EAGLE.

1. Shall I make more space in between these two to approach 85Ohm better?

Spacing depends on your impedance and board specs. I'd go after the impedance calculators values!

General

Length-matching is not at all critical for USB 2.0 or PCI-E 2.X....

PCI-E 3/4 is more relevant.

I'd shoot for an impedance of nom. 87.5 Ohm.

Make sure to use a proper PCB-House, as materials matter!

• Thx. As for USB: I'll use it for low-speed serial communication, so I'm good with it. However, PCIe2.x uses 2.5GHz signals and I quite curious if I have to mess with impedance matching its TX/RX pairs, if those trace lengths are ~13mm. May 11, 2023 at 19:25
• @Daniel For USB it doesn't matter what "Payload" it transfers. It operates at a given frequency. PCI-E intra-pair (TX_n to RX_n) matching is not that critical. Inter-Pair matching (Clock to TX/RX) is important and should be kept in mind - tough PCI-E 2.5 is (compared to PCI-E 3/4) forgiving. Think about it this way: It doesn't matter if TX_1 "arrives" before TX_3, as long as no signal "arrives" misaligned to the clock! Also, you have to differrentiate between Impedance-Matching and Length-Matching. Impedance-Matching prevents reflections. Length-Matching prevents "out-of-timing" problems. May 11, 2023 at 21:01
• @Daniel At aprox. 13mm you are good to go. Avoid using vias (If you have to, place GND Vias close by and don't be conservative with them), keep all Traces roughly the same length +/- 5mm (All signals overall, use the Clock-Line as reference), and make sure to hit your target impedance of 85Ohms nom. to avoid reflections. The last point is the more important one, as impedance mis-match is a frequent cause for EMI-Problems (Big EMI problems due to small problems!). Also make sure to use !proper! decoupling on all Logic-VCC-Rails to avoid EMI problems. May 11, 2023 at 21:05