I simulated a half bridge with two NMOS and at every switching event a current spike up to 1.2 A in the voltage source V4 occurs. I used a resistor as load because with any inductive or capacitive load I would expect a spike because of the dead time between the MOSFETs. Can the parastitic capacitance between Gate-Drain and Gate-Source be the reason or did I do something wrong in the simulation? I know that the selected FETs are oversized but properly I need them for a higher load.

enter image description here


M1 Vsource Vg_HS Vnode Vnode IXFX90N30
M2 Vnode Vg_LS 0 0 IXFX90N30
V4 Vsource 0 100
R3 0 Vnode 1k
V1 Vg_HS Vnode PWL REPEAT FOREVER (0 5 0.00159999 5 0.0016 0 0.0033 0 0.0033000001 5) ENDREPEAT
V2 Vg_LS 0 PWL REPEAT FOREVER (0 0 0.001649999 0 0.00165 5 0.003249999 5 0.00325 0 0.0033 0) ENDREPEAT
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\hamsn\Documents\LTspiceXVII\lib\cmp\standard.mos
.tran 7m

1 Answer 1


Can the parasitic capacitance between Gate-Drain and Gate-Source be the reason

Not quite. It's the Drain-Source capacitance.

If you check the spec sheet, Coss is 1 nF at 100 V.

I eyeballed the switching time to be 0.1 ms. The supply voltage is 100 V.

I = CV / T = 1 nF * 100 V / 0.1 ms = 1 A

That is darn close to the 1.2 A that you see reported.

  • 2
    \$\begingroup\$ Many thanks! With a smaller FET and a slower slew rate it look much better \$\endgroup\$
    – hanss
    May 12, 2023 at 17:55

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.