# Frequency of PCIe differential pairs (RX, TX, CLOCK)

I'm planning to design a board for PCIe (v2).

For all impedance matching considerations, there is rule-of-thumb: if you can decrease the trace lengths below 1/10 of the wavelength, you're probably good to go even without serious impedance matching.

Now looking at those amazing great GT/s values for PCIe versions (5GT/s for v2), I was thinking on how is this really utilized? 5GHz? No CPU is out there which is clocked to this high frequency. And PCIe v4 is even higher (16 GT/s). Is it clocked for 16GHz?

Are these valid states?

1. PCIe v2's differential pairs (RX, TX) is clocked for 500MHz?
2. PCIe v2's differential pair (REFCLK) is clocked for 100MHz? (x1 lane)
3. PCIe v4's differential pairs (RX, TX) is clocked for 123.1MHz?
• That rule of thumb is a) about the trace length, b) the highest frequency content is not given by the clock frequency but by rise/fall times Commented May 14, 2023 at 18:24
• Please don't ask if what ChatGPT says is correct or not. Commented May 14, 2023 at 18:56
• Daniel - Hi, As commented above and as explained in this discussion on our meta, the clear result is that asking about ChatGPT-type responses is not allowed here. Please don't ask about ChatGPT-type responses. Thanks. Commented May 14, 2023 at 20:31
• @SamGibson: thanks for pointing this out. Shall I remove these parts from the question now? Commented May 14, 2023 at 20:35

The trace width being less than tenth of wavelength has nothing to do with the decision if you need impedance matching or not. The rule of thumb applies to length of traces, not width.

And the rule of thumb is not really defined by the wavelength of the signal either, but the rise/fall times of the signal edges, and the allowed impedance mismatches that cause signal reflections.

PCIe V2 is 5 Gbps, so there definitely is a 5 GHz bit clock that clocks bits out at 5 Gbps. It does not require a CPU to run at that speed, the link does. So in theory, there can be signal edges happening at 5 GHz rate even with the 8b10b line encoding. And yes, PCIe V4 is 16 Gbps with 16 GHz bit clock.

Both PCIe V2 and V4 use 100 MHz reference clock, no matter how many lanes are used.

So yes, this is PCIe, you need extremely serious impedance matching, not just for the PCB traces, but for everything, and for the transition areas between everything. This includes even vias, connector pin pads, and pads for any other components there might be on the PCB traces.

And for further understanding, a digital signal is basically a square wave, and you want that square wave to pass through your board with little degradation. The problem is, for any square wave with some bit rate, there is a rule of thumb that you need at least 5 times the bandwidth for the square wave to pass through a system and stay as a square wave. So a 5 Gbps PCIe needs to have a PCB design that can pass 25 GHz without too much degradation in the signal.

• Sorry, I really meant to write trace length! :) Commented May 14, 2023 at 19:27

For all impedance matching considerations, there is rule-of-thumb: if you can decrease the trace lengths below 1/10 of the wavelength, you're probably good to go even without serious impedance matching.

This is only true for narrowband (sinusoidal) signals. It is not applicable here.

A more common rule of thumb for digital circuits is that the length in inches must be less than the rise time in nanoseconds.

Now looking at those amazing great GT/s values for PCIe versions (5GT/s for v2), I was thinking on how is this really utilized? 5GHz? No CPU is out there which is clocked to this high frequency. And PCIe v4 is even higher (16 GT/s). Is it clocked for 16GHz?

The receiver runs at the transfer rate, which for PCIe 4.0 is 16 GHz.

PCIe v2's differential pairs (RX, TX) is clocked for 500MHz?

That is obvious nonsense. Rather than ask a computer to lie to you, I suggest getting a book on high frequency circuit design. There many out there that will discuss how to route PCIe. Without taking the time to understand what you're doing, you're unlikely to end up with a working design.

• By any chance, can you please link a few of those books/resources/videos which are easy enough to start with (without escaping after the first pages)? :) Commented May 14, 2023 at 20:31
• I mean, it is still applicable here -- you just need to include the maximum significant frequency. Which will be a harmonic of the clock, perhaps 7th or more. Commented May 14, 2023 at 20:35
• @TimWilliams The maximum significant frequency is defined by the rise time, not the wavelength, so as a rule of thumb it is not applicable i.e. you need more information than just the wavelength. The calculation works of course if you know the right numbers to use in place of the period of the fundamental though, as you suggest. Commented May 14, 2023 at 20:53
• Yes, to be clear, bit clock in this case. Data may change less often than that, but the maximum rate is to toggle with every bit. Commented May 14, 2023 at 20:57
• @Daniel I think recommendations are not allowed, but you can find many good lectures on PCIe and high frequency routing on youtube. If you find a lecture helpful, you might buy that person's book. There are also many common introductory books recommended for high frequency design that you can find discussed on Google. Commented May 14, 2023 at 20:58