If I understand correctly the process to assemble multi-layer PCBs, two-sided boards are made, with separators intertwined, and they are then pressed together. The two-sided boards have already been etched, which in theory leaves an uneven surface. When pressed together, it then appears to me that one of two things should happen:

a) The thickness of the separating layers is preserved but they suffer deformation, in which case the PCB would end up looking uneven at the end (probably not what happens?)

b) The parts of the separators above copper are pressed more than those above etched areas, thus yielding even surfaces, but with higher densities of separating material. This in turn probably changes the dielectric constant which might cause some (probably tiny) signal integrity issues (I believe?)

Is one of the above two variants correct?

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    \$\begingroup\$ Core stacks are very uniform. Prepreg is less so. (Dielectric constant-wise.) The 2nd reference talks about that: 1 2 3. Regardless, you may find some useful info in those three links. I'll leave it to others to provide a more direct answer. \$\endgroup\$ May 14, 2023 at 22:36
  • \$\begingroup\$ If you NEED a predictable dielectric constant and/or spacing to give you controlled impedance, then you should use lines across core layers, not across pre-preg layers. If you REALLY need a good dielectric, then you can use real RF material instead of FR4 for the RF layers, like RO4350, and still keep costs down by using FR4 prepreg, and FR4 cores for the less important power control and bias layers. \$\endgroup\$
    – Neil_UK
    May 15, 2023 at 5:59

1 Answer 1


The separating layers (normally called "pre-pregs") are fiberglass layers, but the crucial difference is that their resin is uncured when they are pressed together in the lamination process. This means that the resin component can deform and even flow fairly readily.

As they are compressed between two core layers, the resin flows to fill the gaps between the copper areas on the facing surfaces of the cores.

This does cause some variation in the dielectric constant because the resin and the glass have different dielectric constants, so that regions with more resin and less glass have lower effective dielectric constant, and vice versa.

If I have understood your question correctly, I believe this means that both of your "variants" are at least partly correct.

How are layers kept parallel in multi-layer PCBs?

I haven't observed the process myself, but I expect a solid surface is used on either side of the board to apply pressure during the lamination, and this ensures that the board remains flat and the cores remain parallel.

In olden times, it was recommended to maintain roughly equal copper coverage across the board, and between symmetrically opposed layers of the board. Meaning, in a 4-layer stack-up if layer 1 has 70% copper coverage (and 30% of the copper etched away) then layer 4 should also have 70% coverage. Furthermore, any given square cm of the board should have roughly 70% coverage (not 100% coverage on the right 2/3 of the board and 0% on the left 1/3). This was meant to prevent warping of the board as it cooled after the lamination and curing of the pre-preg.

  • \$\begingroup\$ Out of curiosity, why is it no longer recommended to keep copper coverage even? Are modern epoxy formulations just not as susceptible to warping, are there improved manufacturing techniques (like perhaps keeping the board pressed while it cures or something) that prevent warping, or was it maybe just never actually necessary in the first place? \$\endgroup\$
    – Hearth
    May 15, 2023 at 5:22
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    \$\begingroup\$ @Hearth personally, I disagree with the "in olden times" bit and still follow that reccommendation. Not even half a year ago we had a problem with one of our modules at work where the PCB warped significantly (we put it "flat" on a desk and the ends on both sides stood up about 5mm...). In this case this module was supposed to carry high currents -> 6 layers, 3 oz copper, you name it. But the current paths werent distributed evenly and after redoing the layout the issue went away. So I dont think one can generally say this issue was only back then (also we didnt cheap out on the manufacturer) \$\endgroup\$ May 15, 2023 at 6:21
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    \$\begingroup\$ I have also experienced warping on a 2-layer PCB when only bottom side had GND fill (image), so it does happen. \$\endgroup\$
    – jpa
    May 15, 2023 at 9:19
  • \$\begingroup\$ @PatrickFiedler, 3 oz copper is certainly going to make balanced copper fill more important. \$\endgroup\$
    – The Photon
    May 15, 2023 at 15:55
  • \$\begingroup\$ @Hearth, It may be that the reason I haven't run into this issue recently is simply that I've been working on more compact designs (~10x30 mm) where warping is less likely to be an issue. \$\endgroup\$
    – The Photon
    May 15, 2023 at 15:56

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