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I am designing a circuit that uses the 2n7000 NMOS as a switch, controlled by a digital I/O pin from an Arduino Micro.

I made a simulation in LTspice, and I notice that when the NMOS is turning off the drain-source current becomes negative for a very short time: -

enter image description here

Why does this happen? Is it unwanted? Can this be avoided?

The netlist is here. The model for the 2n7000 is not available in LTspice by default, by the way.

XM1 Vin N001 N002 2N7000
V1 Vin 0 3
R_load N002 0 220
V2 Vgate 0 PULSE(0 5 1m 10n 10n 1 2)
R_pulldown 0 Vgate 10k
R_gate Vgate N001 1k
* fetched 2015/3/15 from http://www.onsemi.com/pub_link/Collateral/2N7000.REV0.LIB
.SUBCKT 2N7000 1 2 3
**************************************
*      Model Generated by MODPEX     *
*Copyright(c) Symmetry Design Systems*
*         All Rights Reserved        *
*    UNPUBLISHED LICENSED SOFTWARE   *
*   Contains Proprietary Information *
*      Which is The Property of      *
*     SYMMETRY OR ITS LICENSORS      *
*Commercial Use or Resale Restricted *
*   by Symmetry License Agreement    *
**************************************
* Model generated on Mar 31, 04
* MODEL FORMAT: PSpice
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
*   RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=2.236 LAMBDA=0 KP=0.0932174
+CGSO=1.79115e-07 CGDO=1.0724e-11
RS 8 3 1.10523
D1 3 1 MD
.MODEL MD D IS=2.71011e-10 RS=0.0140826 N=1.5 BV=60
+IBV=1e-05 EG=1.16084 XTI=3.00131 TT=0
+CJO=3.41211e-11 VJ=4.67429 M=0.899864 FC=0.1
RDS 3 1 2.4e+11
RD 9 1 0.0001
RG 2 7 2.18034
D2 4 5 MD1
* Default values used in MD1:
*   RS=0 EG=1.11 XTI=3.0 TT=0
*   BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=7.93181e-11 VJ=0.643298 M=0.9 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.400165 RS=3.00002e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 1.58786e-10
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.400165
.ENDS 2n7000
.tran 0 10 0 1m
.backanno
.end

EDIT

Using the NMOS as a low side switch yields the same results, except now the current is negative when the NMOS turns on:

enter image description here

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3 Answers 3

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These transient current spikes are usually not an issue because it exists only for a few ns.

In your circuit where the switch is used in the low side, this is happening due to capacitive coupling from gate to drain of the transistor. When gate goes high sharply, there will be some coupling to the drain which will increase the drain voltage beyond 3V and hence there will be a reverse current through the load for a very short period.

In your simulation, if you make the rise time and fall time slower, this negative current will reduce. This is just for your understanding.

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Since you are using a NMOS FET as a high side switch, the load current to FET is off even if there is still some gate charge left so there is some Vgs voltage. So when drain current is already zero, what you see is likely the current to discharge Vgs, which has to discharge to 0V.

If your circuit needs a high side NFET for some reason and your load can handle the negative current, it might be fine. It's just that if you want to use a N-FET as a switch for a load, you generally don't use it to switch the positive supply to the load.

And with your new circuit, same thing, but due to gate-drain capacitance.

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  • \$\begingroup\$ Hey @Justme, even if I use the NMOS as a low side switch the current still becomes negative for a short time. Do you think there is a better solution, where the current never becomes negative? \$\endgroup\$
    – Carl
    May 15, 2023 at 7:03
  • \$\begingroup\$ Same thing but with gate-drain capacitance. First there is no current through load. MCU rises the gate voltage and since there is gate-drain capacitanve, the rising gate voltage must cause drain voltage to rise too as it tries to push Cgd current out through drain, and there will be reverse current through load again. \$\endgroup\$
    – Justme
    May 15, 2023 at 7:12
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If you go "very" fast, you should see what happens ...

as pointed by @sai and @Justme (delta t = 1 ps and "model").

enter image description here

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