Rail to rail op amp clipping at output near zero

Question

I am scaling a 10.64 Vp-p (+5.32 to -5.32) signal to ~4.6 Vp-p (0 to 4.6) using an OPA4192 as a differential opamp. The feedback configuration results in attenuation (less than unity gain.) The OPA4192 is a rail to rail opamp. The common mode input voltage and output is within the specified range in the datasheet.

The issue is that when the output goes below 0.5 V it is clipped and the clipped part appears at the inverting input of the opamp (both inputs should be at same potential {virtual ground.}) When I use the same opamp with feedback such that gain=>1 the output goes near 0 V also when it is used as a buffer or comparator.

What am I doing wrong?

The op amp is used with a single supply and the dc offset at non inverting input is 1.6 V to keep the output above or near (0.03 V) ground. Please look at the pictures attached:

1. Schematic.
2. Real time output of op amp on oscilloscope.
3. Real time inverting (yellow) and non inverting (green) input of op amp on oscilloscope.

edit:I am sorry I uploaded the wrong schematic with very low resolution. Also the input would be DC or less than 15Hz signal.

]

Answer 1

and the dc offset at non inverting input is 1.6 V to keep the output above or near (0.03 V) ground.

From the values shown in the schematic it should be 0.8V (assuming the pot is at mid):

$$ \mathrm{V_{off}=\frac{1.6}{8.3+1.6} \ 5=0.81V} $$

And this is not the value you'll get as the output offset. With your configuration it might be difficult to adjust the output offset. I simulated your circuit with AD822 which is a R2R CMOS op amp, played with values and here's what I ended up with (Designators don't match):

The output has 1.64V offset and the peaks at 3.4V when the input is 5Vp.

---

I'd go for AC coupled non-inverting amplifier instead:

^{simulate this circuit – Schematic created using CircuitLab}

R2-R3 pair brings a constant offset of 1.7V. The non-inv amplifier with equal gain setting resistor will bring a voltage amplification of 2. CC2 blocks the DC so the DC offset won't be amplified. This means that the output will have 1.7V offset.

You want the ±5V input signal to be converted to 1.7 ± 1.7V signal. Since the AC amplification factor is 2 (1+R4/R5) the input signal should be attenuated to 0.85V i.e. a factor of 5.88. At AC R2 and R3 will be paralleled so their equivalent will be 6.67k. R1 and this equivalent will form an attenuator. So R1 should be (5.88-1) time R2-R3 equivalent: \$R1 = 6.67k (5.88-1)\approx 33k\$.

NOTE: CC1 and CC2 should be selected for the lowest frequency. For the circuit above the minimum frequency should be around 20 Hz.