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I am scaling a 10.64 Vp-p (+5.32 to -5.32) signal to ~4.6 Vp-p (0 to 4.6) using an OPA4192 as a differential opamp. The feedback configuration results in attenuation (less than unity gain.) The OPA4192 is a rail to rail opamp. The common mode input voltage and output is within the specified range in the datasheet.

The issue is that when the output goes below 0.5 V it is clipped and the clipped part appears at the inverting input of the opamp (both inputs should be at same potential {virtual ground.}) When I use the same opamp with feedback such that gain=>1 the output goes near 0 V also when it is used as a buffer or comparator.

What am I doing wrong?

The op amp is used with a single supply and the dc offset at non inverting input is 1.6 V to keep the output above or near (0.03 V) ground. Please look at the pictures attached:

  1. Schematic.
  2. Real time output of op amp on oscilloscope.
  3. Real time inverting (yellow) and non inverting (green) input of op amp on oscilloscope.

edit:I am sorry I uploaded the wrong schematic with very low resolution. Also the input would be DC or less than 15Hz signal.

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  • \$\begingroup\$ Even at ideal conditions as far as i can calculate you will get clipping when input sine (at V_ctrl?) reaches more than 4.8 V with respect to ground (assuming pot1 is short and you have 1.6 V at noninverting input of u1a). \$\endgroup\$ Commented May 15, 2023 at 9:02
  • \$\begingroup\$ Are you sure R2 is 10k? Where did you get the op amps from? \$\endgroup\$ Commented May 15, 2023 at 9:58
  • \$\begingroup\$ I'd be interested to see the 12V power supply voltage trace, with Vctrl, and to see if anything changes if D1 and C9 are removed. \$\endgroup\$ Commented May 15, 2023 at 11:36
  • \$\begingroup\$ @MakePlatanGreatAgain the datasheet specifies under no load condition to output reaches near zero i would have no worries even if it clips at 100mV but 500mV is too much and doesnt make any sense to me because the output reaches zero when gain >= 1 \$\endgroup\$ Commented May 16, 2023 at 10:11
  • \$\begingroup\$ @AliSiddique Hi, i made that assumption on your previous scheme, which was uploaded wrong as you mentioned, also it is shown in LTspice simulation from Rohat Kılıç \$\endgroup\$ Commented May 16, 2023 at 14:32

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and the dc offset at non inverting input is 1.6 V to keep the output above or near (0.03 V) ground.

From the values shown in the schematic it should be 0.8V (assuming the pot is at mid):

$$ \mathrm{V_{off}=\frac{1.6}{8.3+1.6} \ 5=0.81V} $$

And this is not the value you'll get as the output offset. With your configuration it might be difficult to adjust the output offset. I simulated your circuit with AD822 which is a R2R CMOS op amp, played with values and here's what I ended up with (Designators don't match):

enter image description here

The output has 1.64V offset and the peaks at 3.4V when the input is 5Vp.


I'd go for AC coupled non-inverting amplifier instead:

schematic

simulate this circuit – Schematic created using CircuitLab

R2-R3 pair brings a constant offset of 1.7V. The non-inv amplifier with equal gain setting resistor will bring a voltage amplification of 2. CC2 blocks the DC so the DC offset won't be amplified. This means that the output will have 1.7V offset.

You want the ±5V input signal to be converted to 1.7 ± 1.7V signal. Since the AC amplification factor is 2 (1+R4/R5) the input signal should be attenuated to 0.85V i.e. a factor of 5.88. At AC R2 and R3 will be paralleled so their equivalent will be 6.67k. R1 and this equivalent will form an attenuator. So R1 should be (5.88-1) time R2-R3 equivalent: \$R1 = 6.67k (5.88-1)\approx 33k\$.

NOTE: CC1 and CC2 should be selected for the lowest frequency. For the circuit above the minimum frequency should be around 20 Hz.

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  • \$\begingroup\$ Kilic thankyou for the effort 1) Sorry i uploaded the wrong schematic i have updated it if you could give it a look one more time please. 2 )I simulated OP234 in proteus which is also R2R with the same configuration and it was working perfectly fine. I could not find OPA4192 for proteus simulation. 3) I forgot to mention the input would be DC or very slowly changing frequency not more than 15Hz i am certain it would be a DC signal so i dont want to design it for an AC. 4) I have been asked to attenuate the signal with a feedback config and not use a voltage divider at the input. \$\endgroup\$ Commented May 17, 2023 at 5:02

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