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I am a beginner in electronics with less than 2 weeks of actual experience and less than 6 months of study time.

In figure 1 I drew a circuit implementing the NAND logic, while in figure 2 I drew the actual NAND gate (transistors and resistors) separately from other components (switches, diode, battery) implementing the logic.

I tried the same with AND gat in figure 3 and figure 4. But it appeared to be impossible to separate the actual AND gate from the other components without breaking the circuit. This is because the output of the AND gate is connected in series with the rest of the circuit, unlike the output of the NAND gate which is connected in parallel. So I had to separate the AND gate by NOTting the output of a NAND gate, as can be seen in figure 4. It took me 3 transistors and 4 resistors instead of 2 transistors and 3 resistors.

Is there any way of separating the output of the AND gate made up of 2 transistors and 3 resistors, so that this output can be fed into other logic gates?

  • \$\begingroup\$ What does make fig-1 a NAND gate, and how would fig-3 be an AND gate? \$\endgroup\$
    – greybeard
    May 15, 2023 at 14:29
  • \$\begingroup\$ @greybeard If the circuit depicted in figure 1 is built in breadboard it produces the 1110 truth table of the NAND gate, similarly the circuit depicted in figure 3 produces the 0001 truth table of the AND gate. I have just built them and have confirmed that they actually do. \$\endgroup\$ May 15, 2023 at 14:53
  • \$\begingroup\$ Look up the CMOS "AND" gate implementation. This is the most used implementation these days in VLSI design. \$\endgroup\$
    – sai
    May 15, 2023 at 15:29
  • \$\begingroup\$ you have an inconsistency in fig. 1 and fig. 3 ... fig. 1 output has to be high to light the LED ... fig. 3 the output has to be low to light the LED \$\endgroup\$
    – jsotola
    May 15, 2023 at 15:31
  • \$\begingroup\$ You say truth table, I see bases "receiving" a current or none depending on switches and expect collector currents/voltages to change accordingly, the LED to emit significant light or not: What does make fig-1 a NAND gate? Does this "definition" allow outputs to be connected to inputs? Is fig-3 an AND gate by the same token? \$\endgroup\$
    – greybeard
    May 15, 2023 at 15:56

1 Answer 1


I think the reason this feels nonsensical is that your input and output are different types of logic signals. The input is 5V when high and 0V when low and current goes into the input. The output is 0V when high and 5V when low and current goes into the output. These inputs are not compatible with this output - you couldn't chain two of these gates together.

But who said 5V has to be high and 0V has to be low? As long as you remember the output is reversed, you can still draw a logic diagram for this circuit: it turns on the LED when A and B are both on:

        |    \
A ------| and \
        | gate |---LED
B ------|     /

If you want the diagram to look a little more like the circuit, you could draw your gate as a NAND gate (it's the same gate, after all) and then show the LED wired between the 5V and the output, so the LED turns on when the output is low. You still can't chain these gates because the inputs want to have current put in and the output also wants to have current put in. (You can make that work if you use a low-value pull-up resistor to supply the current to both, but that isn't a very good design as it wastes lots of power)

Also remember the point of a diagram is to tell someone something. If you want to show someone what the circuit does, show them the diagram above (but draw it better). If you want to show someone how it's built, show them the circuit with transistors. There's no need to force both to fit on the same diagram if they don't fit.

  • \$\begingroup\$ Is there something unusual in the ways I am making logic gates? In youtube I also saw logic gates being built in these ways. I can connect output of one into inputs of others for NOT, NAND and NOR gates only. I made an XOR gate using 4 NAND gates ad the following identity XOR (A,B) = NAND ( NAND(A,NAND(A,B)) , NAND (B,NAND(A,B)) ) \$\endgroup\$ May 15, 2023 at 17:24

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