I'm designing a very heavy impedance-requiremented PCB, with PCIe v2.

I know TX and RX diffpairs have strict differential impedance requirements of 100Ohms.

But I couldn't really find impedance requirements for RefClk diffpairs. Are there any?

  • \$\begingroup\$ I don't know, but it would be very surprising if these weren't the same – I mean, same connector, same boards, same circuitry … why would you choose any other impedance? \$\endgroup\$ May 16, 2023 at 16:21
  • \$\begingroup\$ I wish to skip impedance matching on this pair IF I can. :) \$\endgroup\$
    – Daniel
    May 16, 2023 at 16:45
  • \$\begingroup\$ ah in that case, I'm not a PCIe expert, but didn't v2 add the mode "data clocked refclk", so you can omit that all? \$\endgroup\$ May 16, 2023 at 16:51

1 Answer 1


PCIe electrical specs between data and clock lanes are slightly different. All lanes still have the same differential impedance requirement.

So you can't skimp on routing clock lane without proper differential impedance.

If you are not aware, even if specs say 100 ohm differential terminations, routing the tracks with 100 ohms may not be the best option, and many design guides say 85 ohms as the best practice - but it depends very much on if you are making the motherboard or the card or some adapter that sits between motherboard and card.

  • \$\begingroup\$ I'm designing a card which acts as a KeyE M2 card, and provides a KeyM M2 socket to host an NVMe SSD. Traces are quite long to skip the impedance matching (15mm), and as I can see I need to use vias too. Now if I need vias, I need to consider backdrills too, and I would really need a manufacturer who can test the impedance after (or during) manufacture phase to make it perfectly 85Ohms around the required frequency (of 25GHz for PCIe v2). \$\endgroup\$
    – Daniel
    May 16, 2023 at 20:27
  • \$\begingroup\$ Is RefClk diffpair's + and - reversible? Just like PCIe's RX and TX diffpairs? \$\endgroup\$
    – Daniel
    May 16, 2023 at 21:17
  • \$\begingroup\$ +/- can be swapped, that's just a 180 degree offset, and the phase of that clock is not used anywhere. \$\endgroup\$ May 17, 2023 at 2:52
  • \$\begingroup\$ Wait, isn't the PCIe refclock HCSL, while the lanes are LVPECL? \$\endgroup\$ May 21, 2023 at 10:12
  • \$\begingroup\$ @SimonRichter You seem to be right, but it still does not change the answer to question if impedance controlled lanes must be used for clock. \$\endgroup\$
    – Justme
    May 21, 2023 at 17:53

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