I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one rising edge, and my outputs change on.. the same edge? the next rising edge?
if I have two modules, where the output of one flows into the inputs of the next, there could arise the situation where the inputs to my module (the outputs of a previous module) are changing at the same time as they are captured.
The marker at 205ns shows what I'm talking about, op and data_write being my inputs. Everything seems to "just work" in this test case, but in the simulation it's not clear exactly what is being captured when. Is the data_write="0001..." being captured at 205ns or (205ns + 1 clock cycle)? Is there a way to get more detailed waveforms in ISim that show setup and hold times?