Latch is stable with competing capacitors?

Question

I inherited the attached design as part of a work project. This is a latch which is meant to hold the high-voltage side of the system in the powered on state when a momentary power button attached to J3 is pressed.

There are a few transistors off to the right that allow the system to turn itself off but what's important is that the top line going off to the right is the output and determines whether the high-voltage stage is on or off.

As the schematic comment states, when C1 and C2 are populated the system will be in the OFF state when 5VL is energized, if default ON is desired C10 and C11 should be populated. Straightforward enough.

What puzzles me is that the example assembled version of this board that I was given with the schematic has all four of these capacitors populated and still always powers up with the high-voltage stage OFF. How can this be? Shouldn't the two sets of caps be fighting each other putting the latch back into the same metastable state it would have been in if there were no capacitors at all? Did this particular version of the board just get lucky with the tolerances of the capacitors or is there some other effect that explains this behavior I am not considering?

Thank you for the education!

Answer 1

If all 4 caps are populated, then, the output state when the 5VL is energized will depend on the asymmetry in cap values & also on the following
a. parasitic capacitances on the nets
b. mismatch between Q7 & Q8
c. mismatch between R10 & R11

Since most of the above factors can vary from one board to another, we cannot predict the latch output state for all the boards upon powerup. In this board you were lucky to have the default state to be power off. Very difficult to guarantee that all boards will behave the same way. The default powerup state could possibly change across temperature also. So, you should not have all the 4 capacitors populated.