# What percentage of a DRAM cell size is occupied by the transistor and/or the capacitor?

Assuming that we have a 1T1C DRAM cell manufactured at 22nm process. Based on this we can have an idea about the cell area (0.026 um^2 in this case). However, I could not find specific information about the percentage of the area consumed by the transistor and the capacitor, respectively. What makes it a bit more difficult is the fact that different type of capacitors could be used in different cells (trench or stacked). Since I'm not a device engineer myself, does anyone know some ballpark numbers on this (or maybe where can I look for - to deduct these number from)?

EDIT: I found the "CMOS VLSI Design" book by Weste and Harris in my library, back from my student years. The following image leads me to believe that since the trench capacitor is extended on the 3rd dimension "under" the drain n-well, it has no real impact on the area - or am I wrong?

• I can’t immediately answer your question but I can tell you that 22nm tech means that the smallest feature size is 22nm, so I would expect a RAM cell to be several times that size.
– Frog
Commented May 21, 2023 at 19:41
• blocksandfiles.com/2020/04/13/…. This source estimates the area to be 6 to 8 times the area of the feature size squared.
– Frog
Commented May 21, 2023 at 19:44
• @Frog Sure,but 0.026 square micrometres is an area corresponding to a 161 nm by 161 nm square, for example. So that matches what you wrote fairly well. Commented May 21, 2023 at 19:47
• @Frog Please see my edited question, it might add something useful Commented May 21, 2023 at 20:01
• I just found out that the process to create eDRAM is completely different than "normal" DRAM. So let me rephrase: in "regular" DRAM, what percentage of the cell area is being occupied by the capacitor? Regardless of the process used. Commented May 21, 2023 at 22:29