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Assuming that we have a 1T1C DRAM cell manufactured at 22nm process. Based on this we can have an idea about the cell area (0.026 um^2 in this case). However, I could not find specific information about the percentage of the area consumed by the transistor and the capacitor, respectively. What makes it a bit more difficult is the fact that different type of capacitors could be used in different cells (trench or stacked). Since I'm not a device engineer myself, does anyone know some ballpark numbers on this (or maybe where can I look for - to deduct these number from)?

EDIT: I found the "CMOS VLSI Design" book by Weste and Harris in my library, back from my student years. The following image leads me to believe that since the trench capacitor is extended on the 3rd dimension "under" the drain n-well, it has no real impact on the area - or am I wrong?

DRAM cells design

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  • \$\begingroup\$ I can’t immediately answer your question but I can tell you that 22nm tech means that the smallest feature size is 22nm, so I would expect a RAM cell to be several times that size. \$\endgroup\$
    – Frog
    Commented May 21, 2023 at 19:41
  • \$\begingroup\$ blocksandfiles.com/2020/04/13/…. This source estimates the area to be 6 to 8 times the area of the feature size squared. \$\endgroup\$
    – Frog
    Commented May 21, 2023 at 19:44
  • \$\begingroup\$ @Frog Sure,but 0.026 square micrometres is an area corresponding to a 161 nm by 161 nm square, for example. So that matches what you wrote fairly well. \$\endgroup\$
    – TooTea
    Commented May 21, 2023 at 19:47
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    \$\begingroup\$ @Frog Please see my edited question, it might add something useful \$\endgroup\$
    – Arkoudinos
    Commented May 21, 2023 at 20:01
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    \$\begingroup\$ I just found out that the process to create eDRAM is completely different than "normal" DRAM. So let me rephrase: in "regular" DRAM, what percentage of the cell area is being occupied by the capacitor? Regardless of the process used. \$\endgroup\$
    – Arkoudinos
    Commented May 21, 2023 at 22:29

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Responding to your revised question in the comments, essentially the entire cell area is covered in capacitors:

enter image description here

(Taken from this article: https://www.stinstruments.com/microelectronics/ultra-high-resolution-sem-observation-of-dram-capacitors/ )

In cross section you can see why:

enter image description here

(Taken from this video: https://www.youtube.com/watch?v=Bln-v9LmZ3E )

The capacitors are built on top of the metalization, which is on top of the transistors. As a result of this 3D stacking, the capacitor layer does not have to share space with anything else (aside maybe from a bit of dead area due to the hexagonal packing).

This is in contrast to the (much less common) eDRAM cells linked above, which are made on a (modified) logic process rather than a DRAM process. Since they have to fit into chips logic (e.g. for CPU cache), they're more awkwardly tucked into either the metal wires or etched into the silicon below the transistors and can't be packed as tightly (although as cache they're also usually designed to be fast rather than as dense as possible).

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