Short answer: inductor ripple is more or less irrelevant. Look elsewhere for EMI issues.
There are also reasons why you might not be able to reduce the inductance, anyway. Integrated regulators typically have control schemes (peak current mode control, most importantly), and fixed compensation, such that a ripple fraction below say 30%, or more than 100% at nominal ratings, causes undesirable behavior, or even malfunction.
But assuming a flexible design (or early enough in the design process that this is a consideration), what then?
There is missing context here, so let me illustrate what EMI is concerned with:
simulate this circuit – Schematic created using CircuitLab
Say we have a basic circuit like this. We have full (">100%") ripple current at the input (to C1 and V1), and continuous current (or a ramp waveform, anyway) at the output (to C2 and RL).
What reducing the current ripple will do, is reduce the low-frequency (near Fsw) ripple at the output, proportionally, and the input slightly (since it goes from, say, "120%" ripple, to "110%", but only down to "100%" for infinite inductance).
A reduction in input peak current has a small effect on its EMI, because the peak current change is slightly lower. Since the current is square-wave (well, trapezoidal, but square is equivalent for EMI purposes), the amplitude of harmonics is proportional to the delta.
In any case, suppose we put arbitrarily strong filters on the input and output (more than just C1 and L1-C2). We can reduce DM (differential mode) as far as we like, by choosing filters with F0 at some fraction of Fsw, and as high of an order we like. But we can still have EMI problems. How?
simulate this circuit
Consider this schematic, with two important changes:
- The input and output cables are replaced with bias tees (LC networks). For this purpose, these are called LISNs (line impedance stabilization networks). The RF ports are represented by termination resistors R1-R4; these would be RF connectors, and in general, any of them might instead be a transmitter (for immunity/susceptibility testing), receiver (for emissions testing), or terminated (an actual resistor).
- Ground has been floated, and a few parasitics added: C5, C6 and LG.
Note the effect of the parasitics: the shown values are arbitrary, and they could be in more places than these. The point is more to get you to think about where possible offsets could arise from, and thus, some ground loop voltage exists between connectors. In this case, it's directly across the switching loop, so no matter how carefully we filter the DM, we are left with the same CM voltage.
Thus, DM filters are necessary, but not sufficient, to improve EMI.
Ground loops exist in PCBs, between components, along traces, across ground pours, etc. It can be avoided by making tight loops (place C1, M1, D1 very close together), and keeping connections away from those loops. (Instead of routing across the board, with a layout arranged like the components on this schematic, consider putting the connectors on the same side of the board, so that their grounds can be shorted together locally.)
Stray capacitors can exist between the board and its surroundings (C5 is here expressing the circuit-ground-to-surroundings or PCB self capacitance), and between circuit nodes and circuit ground or connectors by capacitance from components, heatsinks, etc. A common source of EMI is the capacitance on a transistor's heatsink tab, which might only be a few pF, but that's more than enough when the switching voltage is say a few hundred V, and the EMI threshold is only a few mV. (If this were a synchronous converter, so D1 is a MOSFET, its tab would have exactly the effect given by C6, assuming the heatsink were earthed.)
The bias tees may also be called CDN (coupling-decoupling network), AMN (artificial mains network), etc., depending on construction, and the test being performed. In any case, their purpose is to present a well-known impedance to the circuit (EUT, equipment under test) side, while keeping noise (whether emissions or test signals) away from the sources/loads (auxiliary equipment), and communicating high frequencies between EUT and the test equipment.
Thus, although the circuit has expanded, we've reduced the problem. Instead of trying to reason about an arbitrary, noisy, random impedance circuit, we've abstracted it down to a collection of RF ports, with bias voltage/current passed in, and we characterize the RF response between those ports:
simulate this circuit
If we wish to characterize DM, we can subtract VIN and GNDIN, or VO and GNDOUT, and measure that specifically. For CM, we average the pairs instead. Note that, when we average the input and output pairs individually, we are left with a two-port, where the EUT looks like a series element between CM ports:
simulate this circuit
The same is true for DM of course. And we can do both simultaneously, using superposition. Typically, a balun transformer would be used on each pair of ports, so that DM (port 1 - port 2) and CM (port 1 + port 2) are obtained simultaneously.
We could even measure the transfer function of the EUT (from port 1 to port 2, or vice versa, and in whatever N/CM/DM mode we like); though this isn't very interesting for most EMI testing purposes.