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I am trying to determine the sizing of transistors in the OTA as shown below, using the gm/id methodology. I wanted gm1 and gm2 to have much larger gm than the other transistors to reduce noise. I made M1 and M2 have a gm/id of 22.5 and 2.5 for the transistors in current mirrors. Ibias was set to 8uA, so gm1 and gm2 are about 90uS (4u*22.5).

enter image description here

The problem is that I got a smaller Gm (only 71uS) at the output (I got this result from an AC simulation, in which I divided the AC current at the output by the AC voltage at v-, while v+ is grounded). I was expecting it to be close to gm1. I examined the DC operating points, which is shown below. I found that some transistors in the current mirror (M5, M8 and M6) have very small Vds, only a little bit larger than the vdsat. I thought this was the reason of the small Gm, but then I calculated the Gm in this situation as follows (I got the values of gm in a DC simulation):

\$ G_m = \frac{1}{2} \cdot [\frac{gm1 \cdot gm5 \cdot gm8}{gm3 \cdot gm7} + \frac{gm2 \cdot gm6}{gm4}] \$

And the result was 87.25uS instead of 71uS. After I noticed the small Vds was suspicious, I tried to make (W/L) of the current mirrors a bit larger, to increase the gm/id and decrease the larger Vgs consuming much voltage headroom. Then the Gm did increase to gm1.

My question is why the calculations above do not agree with the results and how to explain the drop in Gm. Besides, how to consider Vds in the gm/id methodology.

enter image description here

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Your equation for Gm is valid only if RDS of the transistor is very high. When the transistors say M5, M8 & M6 are at the edge of saturation i.e., VDS just equal to VDSAT, RDS could be low and hence the effective GM will drop as explained in the example below.

Take for eg., M5 & if RDS5 is comparable to 1/gm7, the signal current will not flow into M7 fully. This is the problem you are seeing.

If you make M5's W/L higher for the same ID, VDS will become greater than VDSAT and that will improve RDS and hence almost all signal current will flow into M7 in this case and your calculated GM will match simulation results.

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  • \$\begingroup\$ Thanks for your answer! I am clear about where the problem lies now. So is there any rules or experience like how large the (VDS-VDSAT) should be in a typical design? Or did I miss anything in the design process? \$\endgroup\$
    – George Guo
    May 23 at 3:08
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    \$\begingroup\$ Typically having VDS-VDSAT > 100mV is a rule of thumb. It is not a hard and fast rule. We could start with this and simulate the circuit to see if any more improvement is needed. Then, you can go back and tweak the sizes and/or operating points. \$\endgroup\$
    – sai
    May 23 at 5:23
  • \$\begingroup\$ Hello @sai, can I ask another question? I'm trying to make the length of M5 larger to increase RDS5 while operating at the edge of saturation (I'd also keep gm5 constant). Do you think it's possible to put 2 transistors in series to obtain an equivalent long-channel device to replace M5? I'd like to do this because the maximum length in my process is only 20uM. \$\endgroup\$
    – George Guo
    May 25 at 10:42
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    \$\begingroup\$ Ideally, if you have an extra question, you have to write a fresh question but, since this is a related question I am answering it. Yes, it is a standard practice to put 2 or more transistors in series to increase length when there is a length restriction. However, hope you will also do the same with M3, M4 & M6 when you change M5. BTW, if you are already operating M5 at the edge of saturation, increasing length will not increase RD5 because VDSAT will increase and the device will be go into triode region. \$\endgroup\$
    – sai
    May 25 at 12:46

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