How is a CAN bus like an AND gate?

Question

In this PDF, I read this line:

This means that the bus can be thought of as acting like an AND gate: If any node writes a dominant (0) bit on the bus, every node will read a dominant bit regardless of the value written by that node.

What does this mean? Like, the node has already written 0 on the bus, so how does the phrase "regardless of the value written by that node" make sense here?

Also, I get the comparison to AND gate in the sense that if a node writes 0 and another node writes 1, the bus reads 0 via the process of CAN arbitration, but could someone explain this comparison more clearly?

Answer 1

When you map the CAN bus state into a truth table, you get following:

This is the same logic you'd get for a n-channel AND gate.

As the term suggests, a dominant bit will always overrule a recessive bit.

Answer 2

I'll try to explain using this simplified structure below:

^{simulate this circuit – Schematic created using CircuitLab}

^{Note that the CAN Bus physical layer is not actually like shown above but it's good enough for simple explanation.}

The transmit transistors are off by default, so the idle state of the bus is 1 thanks to the pull up resistor, Rp.

Each node has TX and RX sub-circuit connected to the bus. This brings error checking (collision detection) e.g. if a node releases the node by turning of the transmit transistor (Qn) it should read logic-1 with its RX buffer.

Now when a node wants to initiate a transmission, it turns on the respective transmit transistor (Qn), pulls the bus low so all the other nodes see this with their RX buffers and switch to their "listening" mode.

Now if two nodes start to transmit right at the same time, if one sends logic-0 (by pulling the BUS low) while the other sends logic-1 (by releasing the BUS), the RX buffer of the latter will not read logic-1 because the bus is held low.

So if one sends logic-0, the bus is held low. Hence the AND behaviour.

For some details see my answer here.

Answer 3

The signals on a CAN bus are similar to those of the i2c: essentially, a "wired AND".

There are different nodes which when idle (or when writing "1"), leave the line floating (driven by open drain / open collector) - which does not float because is pulled up by a resistor.

At this point, any node reads "1". But if a node, or more than one, writes "0", the line goes down, and there is no way for another node to actually write "1", because of the open drain driving.

Now: every node monitors the line. The one(s) which wrote "0" know that the line should read "0", but all the others which didn't write "0" now know that another node is "dominant" and relase the bus (abort the transmission if one was in progress). This permits to propritize the different (kind of) messages: those with many "0"s in the start have greater priority.

Answer 4

An AND gate logic table would be like this:

AND gate (x and y are input pins)

x  y  out
0  0  0
0  1  0
1  0  0
1  1  1

Now if we instead say that x and y are two nodes trying to pull the CAN lines as part of CAN bus arbitration, then we can note that a 0 bit is dominant on CAN and a 1 bit is recessive. That's exactly the same logic table as above.