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I'm doing a Keysight ADS demonstration and it seems to show stitching vias between ground and power planes. The PCB is an 8-layer PCB (the Texas Instrument PandaBoard) with two planes, a ground and power plane. I've understood stitching vias to mostly be ground-to-ground. Is it normal to run stitching vias between GND and PWR, would that not simply short circuit the PCB, and am I entirely misreading what the 3D model below shows?

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Have not worked with stitching vias at all before but I think the idea of that they provide a ground path when there are multiple ground layers seems pretty straight forward. But, stitching between GND and PWR I do not understand.

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No you wouldn't stitch between power and ground, as you suspected that would just short the power out. The power vias might go through the ground planes and the ground vias through the power planes but they wouldn't have connections to each other.

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In short: no, you would never short two planes of different DC potential together with vias.

Your understanding of the return current through the GND vias in your hand-drawn diagram is correct; stitching vias are used near a signal transition from one reference plane to another to ensure small return path.

I suspect one of two things are going on:

  1. There is a mistake in the layer definition: both layers were supposed to be labelled as GND.

  2. An abstraction is being made for the sake of "simplicity": you can stitch planes of different DC potentials together with a capacitor in between, as close as possible to the transition. This allows the high-frequency AC return path to go through the capacitor, without shorting the two planes together. For the sake of a demonstration, the author may have omitted this from the simulation setup and assumed that this would have roughly the same performance as if both the planes were GND and tied together with vias, but in reality the performance will be different (real capacitors have package inductance and ESR).

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