Tie an input of an AND gate to its output

Question

Let's say we have an AND gate and we give 1 as one of its inputs and we tie the other input to the gate's output. What will happen?

Answer 1

Depends on the initial state of the output!

Output is LOW at t0

Now your input signals are LOW and X... AND requires two HIGHs....So the Output will remain LOW independent of any change on X

Output is HIGH at t0

Now your input signals are HIGH and X. If X turns out to be HIGH at t0 as well, the output will stay HIGH until X goes LOW.

But, now (Output went HIGH to LOW) it will never be able to go back to HIGH again.

Transient Case

In case of a real system beeing powered on nobody can really tell. The Output could glitch HIGH for a brief period before going LOW...Even if your X input is LOW all time.

Steady state

Assume your system is powered up and running in a steady state with the output beeing LOW and the input beeing LOW. If you change your input to HIGH nothing will happen - the output will stay LOW.

Answer 2

The wealth of SE EE

I have always said that the biggest asset of SE EE is not the answerers, but the questioners because what we explain can be found in sources but such original, interesting and thought-provoking questions cannot be found there.

Now, in this particular case, what a wonderful question that is! Perhaps a century ago, the inventors of latches and flip-flops asked themselves that and so invented them? If they were not, there would not be flip-flops, RAM, registers, computers, smartphones, internet, web, SE EE... and we would not be here...

Possible ways to answer

If you know what a "latch" is

It is a great idea to see the familiar old in the unknown new. Then the answer to the OP's question is extremely simple - it is just an RS latch (flip-flop if you prefer), only it is missing one input (S). But still it is a latch that fulfills its main purpose of storing data.

If you do not know what a "latch" is

... or you know but do not see the connection to this question, the best answer for you will be to build the circuit of an RS or R'S' latch (the apostrophe means inversion) step by step from the very beginning to the end, revealing at each stage the need to add a new element.

Ok, let's assume this is your case. Even if it is not, let's assume it is because the benefit is great - we are going to do something new that has not been done before. Instead of using trite "explanations" such as "this is...", we will explain exactly "why this is so".

Revealing the truth about latches

I actually did this a year ago in my answer to a related question but now I have the chance to do it by means of CircuitLab.

The most elementary memory cell...

... with hysteresis...

The greatest challenge in circuitry is to make something out of nothing; then it is an invention:-) Such an "invention" would be to make the simplest 1-input logic gate (buffer) "remember".

^{simulate this circuit – Schematic created using CircuitLab}

If the element has multiple inputs (e.g., a 2-input NAND), we can simply join them.

^{simulate this circuit}

If we investigate the behaviour of such a CircuitLab element by driving it with a triangle-shape input voltage, we will see something interesting - it has two input thresholds (VL = 2 V and VH = 3 V).

Ah... that means the element has the so-called "hysteresis" or, in other words, "memory". So we can make a latch (flip-flop) with it without any extra elements, just by driving it appropriately.

^{simulate this circuit}

This means that we can set it by briefly applying +5 V and reset it with 0 V but the rest of the time we must apply 2.5 V (the middle between the two thresholds)...

... and the element without memory already remembers.

... with positive feedback

However, if the element has no hysteresis, we can apply another trick called "positive feedback". Thus, if we connect the output of a non-inverting amplifier or a digital buffer to its input (the OP's idea), it becomes the most basic element with memory aka "latch" or "flip-flop". Thanks to this "self-reinforcing" positive feedback, it can only be in one of its two end states - LOW and HIGH.

^{simulate this circuit}

To understand how this "magic" happens during the transition between the two states, you need to think of this fast digital device as a slow analog device (integrator) that seeks equilibrium but never finds it and finally reaches the supply rails. So this device is an amplifier but it never works as an amplifier (in active mode); it works either as an integrator or it is saturated.

... controlled by one source

To change the state of this memory cell, we must "pull" the output of the amplifier "down" or "up" and then leave it alone (disconnected from the input source). This is a rather "brutal" action because there is a conflict between two voltage sources (the amp output and the input source), but still it is widely used in computer RAMs. We can do (assemble) such a "3-state pulse input source" in the CircuitLab simulation by connecting two oppositely acting pulse input sources R' and S (CSV) through decoupling diodes to the amp output. So they will be switched off when they are not active and the cell will remember undisturbed.

^{simulate this circuit}

Let's see it by the help of the time-domain simulation in the graphs below.

At 5 ms, the input source S briefly (for 5 ms) "pulls up" to 5 V the amp output through the diode D2, and then returns to ground so D2 is off.

This forces the amplifier to go high and feed itself a 5 V at the input, thus maintaining itself in that HIGH state.

At 30 ms, the input source R' briefly (for 5 ms) "pulls down" to ground the amp output through D1, and then returns to +5 V so D1 is off.

This forces the amplifier to go low and feed itself a 0 V at the input, thus maintaining itself in that LOW state (see the graph above).

... via separate input

Here we remember that apart from 1-input there are also 2-input logic gates, and we can use a separate control input. Obeying the OP's wish, we take a 2-input AND logic gate and connect its one input to the output and apply an input pulse signal Vin to the other.

^{simulate this circuit}

... with initial setting

But a problem appears - the cell is initially set by CircuitLab in the zero state and the AND input can change (reset) the output only in the zero state (property of the AND logic function). Then let's add another setting pulse voltage source Vset that "pulls up" the output in the beginning of the simulation.

^{simulate this circuit}

At 5 ms, the initial setting source Vset briefly (for 5 ms) "pulls up" to 5 V the amp output through the diode D, and then returns to ground.

This forces the amplifier to go high and feed itself a 5 V at the input, thus maintaining itself in HIGH state.

At 30 ms, the input source Vin sets the output to zero and after that it loses its control properties.

Cascading ANDs

A new "powerful" idea comes to us - to introduce a second input signal Vin2 by including another logic gate AND2 after the first one... and this way we take a decisive step towards the "invention" of the famous RS latch.

^{simulate this circuit}

But that does not change things because both inputs act the same way (in the same direction) and everywhere along the positive feedback circuit the voltage is 0 V; the circuit is locked.

Cascading NANDs

We are already aware of the problem - the states of the inputs and outputs must alternate, and this means using NAND logic gates.

^{simulate this circuit}

At 10 ms, the input Vin2 toggles the latch (Vout1 = 0 V, Vout2 = +5 V) and loses its control properties. Next time we have to use Vin1 to toggle the latch.

At 30 ms, the input Vin1 toggles the latch (Vout1 = +5 V, Vout2 = 0 V) and loses its control properties. Next time we have to use Vin2 to toggle the latch.

Conventional schematic

Thus we get the ubiquitous RS (R'S') latch. Before we show our "invention" to others, let's draw the circuit in the conventional "cross-coupled" way. But we know that it is cross-coupled just because it is drawn in such a way.

^{simulate this circuit}

The results of the time-domain simulation are the same as above.

Conclusions

• The simplest possible latch can be made with only one logic gate (without any external elements) if it has input hysteresis. It has to be controlled by an input signal with three levels - 0 V, 2.5 V and 5 V.

• Another simple latch can be made with only one (AND or OR) logic gate by connecting one of its inputs to its output (the OP's idea) but it also cannot be controlled with conventional (referenced to ground) input signals.

• It can be controlled by only one input signal with three states - two active (low and high) and one passive (disconnected aka "high impedance").

• To control the latch by two referenced to ground input signals, we have to connect (cascade) another logic gate.

• The two cascaded logic gates cannot be non-inverting (AND or OR); they must be inverting (NAND or NOR).

• This so-called R'S' latch is controlled by two input signals with three states - two active (R' = low, S' = high; R' = high, S' = low) and one passive (R' = high, S' = high).

Answer 3

The result is influenced by the analog nature of the otherwise binary device.

The output is one of the inputs. So there will always be two inputs. During the day power-on transient the gate will act as an amplifier with positive feedback. There will be either oscillation or latching in one direction. It may be predicted with good knowledge of the internal circuit.

If (after power-up) one input is high and the other stable, switching the other input to the output will likely retain the same state, then positive feedback will latch the state.