# Working and simple applications of PLL [closed]

Recently I am studying about Phase Locked Loop. My professor said that it is an amazing device with a variety of application. I understood the basic working of a PLL. But I couldn't appreciate his statement. Can anybody make me understand it's operation by giving a practical example..?

• Wikipedia has a lot of explanations about its operation as well as practical examples of its use: clock recovery, deskew, clock generation, etc etc etc Apr 24 '13 at 18:44

Perhaps one of the most useful applications for a PLL is a frequency multiplier.

A PLL is a feedback loop. Feedback loops try to attain a steady state in which the input is equal to the output. By modifying the feedback mechanism, you can do a lot of interesting stuff...

Consider the following:

Let's say a frequency of 1MHz goes into the Pre Divider set to divide by 1. This 1MHz enters one of the Phase Detector inputs. Now suppose the Feedback Divider is set to, say, M = 8. This 1/8th of MHz enters the second Phase Detector input.

Because the loop is trying to reach a state in which the two inputs are equal, the VCO frequency will eventually have to rise to 8MHz. You just turned 1MHz into 8MHz using a couple of dividers and a VCO.

You'll find a PLL multiplier in every ARM microcontroller. Using a set of various dividers for N and M you can generate many different frequencies from a single clock source.

This is very much an idealistic description followed by a couple of practical examples.

A PLL in it's common form is a phase detector that controls the frequency of an oscillator. The oscillator output is usually a single frequency squarewave.

The phase detector receives 2 inputs and produces an output level that is nominally centre-rail when the phase of the two inputs are exactly at 90 degrees to each other. If the frequencies are different you get a complex signal whose average level will be higher or lower than centre rail.

This allows you to compare two frequencies and get a measure of which input frequency is the highest.

If you feed the output from the oscillator (that is controlled by the phase detector) into one of the phase detector inputs AND you apply an unknown signal into the other input, the PLL will try to adjust its own oscillator so that it matches the input signal frequency but 90º phase shifted.

So what? Not a big deal in doing that you might say BUT, if the unknown input frequency was quite "dirty" with noise and distortion, what you get is a cleaned-up version from the PLL's oscillator. That can be useful.

Because you can choose to filter the output of the Phase comparator to remove high frequencies, if the "unknown input" were frequency modulated, the output of the oscillator would be restricted from following the modulations but, would be representative of the unmodulated carrier frequency of the "unknown input". Useful in radio receivers.

On the other hand if you allowed the PLL to "track" the frequency modulations of the input, the output of the phase comparator (not the oscillator) would look like the signal that originally modulated the input. The PLL is now a frequency demodulator.

The descriptions above are fairly simple and I haven't made any attempt to describe the details that must be covered to succesfully design a PLL.

They're used a lot in integrated circuits to generate clocks at various speeds from a single master clock. It's convenient to have only one actual timing crystal in the design, then generate others at higher frequencies from that.