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I have been taught that when an interrupt arrives, the following generally happens:

  1. The current instruction finishes.
  2. The interrupt is acknowledged.
  3. The hardware state(PSW) is stored .
  4. The PC is updated with the interrupt service routine location (from the vector table).
  5. The software disables interrupts.
  6. The state is stored.
  7. Interrupts may be re-enabled; the service routine begins.
  8. After finishing, the software state is restored.
  9. The interrupts are re-enabled (if not already done).
  10. PSW and hardware restored.

My question is about 4. Where is the state of the process word stored: is there a stack or is it stored in memory? What happens then if multiple interrupts come in: is the psw overriden?

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    \$\begingroup\$ If you want to go insane, look at what happens on the DEC Alpha. It's unique and will drive many people bat-crazy. In short, there is no standard here. Designers can be quite creative. \$\endgroup\$ May 27, 2023 at 10:56
  • \$\begingroup\$ In addition to the answer, if there are multiple interrupt sources active at once, there are a number of mechanisms that have been implemented over the years. From the software having to poll each interrupt source to find out who interrupted. The poll sequence determines who gets higher priority. Others have hardware to determine the priority and select a vector to determine where to jump to the service routine. And there’s more. For a modern example, look at the ARM docs for their Cortex M4 architecture. Hopefully that should answer your questions. \$\endgroup\$
    – Kartman
    May 28, 2023 at 2:22
  • \$\begingroup\$ Many ISA use a combination of hardware stacking and software stacking. The hardware might just stack the PC and maybe some flag register - if you want more than that, it might be a software issue. Now if you program in C, you don't have to bother about ISR calling convention because then the compiler handles stacking for you. If you program in assembler, you can stack as much/little as you like (just remember to pop it too, like always). \$\endgroup\$
    – Lundin
    May 29, 2023 at 14:05

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What happens depends on CPU architecture.

Some store it, some don't and you have to store it yourself. Typical place is stack which is in memory, but you can store it anywhere you want, in a register or memory.

Some architectures disable interrupts and so you never get nested interrupts. Some allow nested interrupts. Some allow programmer to decide what to do. Nesting can be implemented simply by pushing PSW to stack.

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  • \$\begingroup\$ Thank you, is this stack separate to the stack for any program? \$\endgroup\$ May 27, 2023 at 11:50
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    \$\begingroup\$ It again depends on CPU. It may be hardware stack, or the same stack used for everything, or the programs may switch stacks and there may be a separate stack for every task in a multitasking system, or the global stack for the OS itself instead of task local stack. If you have a specific CPU in mind, documentatìon tells you how it works. \$\endgroup\$
    – Justme
    May 27, 2023 at 12:04
  • \$\begingroup\$ Is there another stack for the software registers too? \$\endgroup\$ May 31, 2023 at 17:25
  • \$\begingroup\$ @ThomasStokes It depends on the architecture and more importantly, what you even mean with software registers - usually a CPU has hardware registers. Do you have a specific CPU architecture in mind? \$\endgroup\$
    – Justme
    May 31, 2023 at 17:28
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    \$\begingroup\$ Which program you mean, on which architecture? If you would please refer to a specific architecture you would get a specific answer. That is also architecture specific. Either register values are stored automatically by hardware or program itself must push the registers to stack or store them wherever possible or just decide not to use same registers in different contexts. I don't know what your program does and on what architecture it runs on. \$\endgroup\$
    – Justme
    Jun 2, 2023 at 4:42

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