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Creating a SystemVerilog module called fileRegister which has three 4-bit inputs, and one bit clock, and one bit writeEnable. It should be like figure1 below.

figure1

I'm taking inputs from named data input which has parsed as 2-4-4-4. First 2 bits are Instruction (ALU_Control) other bits are inputs (A1,A2,A3). I wrote a testbench for my module but I got problem with the WD3 (write data, its input bits are result of ALU). My testbench shows its value like X. I haven't figured out how to solve this problem yet. Any help would be greatly appreciated.

My main module:

module fileRegister (
  input logic [13:0] data,
  input logic clock,
  input logic WE3
);
  reg [31:0] file_register[31:0];

  logic [31:0] WD3;
  wire [31:0] Result;
  wire [3:0] ALU_flag;

  logic [1:0] ALU_control;
  logic [3:0] A1, A2, A3;
  logic [31:0] RD1, RD2;

  assign ALU_control = data[13:12];
  assign A1 = data[3:0];
  assign A2 = data[7:4];
  assign A3 = data[11:8];
  assign WD3 = Result;

  always @(posedge clock) begin
    if (WE3)
      file_register[A3] <= WD3;
  end

  assign RD1 = file_register[A1];
  assign RD2 = file_register[A2];

  alu alu_inst (
    .A(RD2),
    .B(RD1),
    .ALU_control(ALU_control),
    .Result(Result),
    .ALU_flag(ALU_flag)
  );

endmodule

My ALU module:

module alu(input  logic [31:0] A, B,
input  logic [1:0]  ALU_control,
output reg[31:0] Result,
output reg[3:0]  ALU_flag);

    wire [31:0] mux2_output;
    wire [31:0] sum;
    
    MUX2 k_0(B,~B,ALU_control[0],mux2_output);
   
    NbitFulladder add(A,mux2_output,ALU_control[0],sum,cout);
    
    MUX4 j_0(sum,sum,A&B,A|B,ALU_control,Result);
   
    assign ALU_flag[3] = Result[31]; //Negative 
    assign ALU_flag[2] = (32'b0 == Result); //Zero 
    assign ALU_flag[1] = cout  & ~ALU_control[1]; //Carry 
    assign ALU_flag[0] = ~(A[31] ^ B[31] ^ ALU_control[0]) & ~ALU_control[1] & (A[31] ^ sum[31]);
    //Overflow

endmodule

My NbitFullAdder module:

module NbitFulladder(
  input logic [31:0] a,
  input logic [31:0] b,
  input logic cin,
  output logic [31:0] s,
  output logic cout
);
  wire [31:0] c;
  genvar i;
  
  generate
    for (i = 0; i < 32; i = i + 1) begin : gen_fulladder
      fulladder i_fulladder (a[i], b[i], (i == 0) ? cin : c[i - 1], s[i], c[i]);
    end
  endgenerate

  assign cout = c[31]; // Carry out (cout) is at index 31
endmodule

and my testbench:

module fileRegisterTB();
logic [31:0] wd3;
logic [13:0] data;
logic WE3, clock;

fileRegister dut(
   .data(data),
   .clock(clock),
   .WE3(WE3)
   );

    initial begin
       data = 14'b00101101011111; WE3 = 1'b1; clock = 1'b1; #10;
   
       data = 14'b01010111110000; WE3 = 1'b1; clock = 1'b1; #10;
       
       data = 14'b10011100001111; WE3 = 1'b1; clock = 1'b1; #10;
       
       data = 14'b11111111111111; WE3 = 1'b1; clock = 1'b1; #10;
       
       $display(wd3);
    end
    
endmodule

My MUX2 Module:

module MUX2(input logic [31:0] d0, d1,
input logic sel,
output logic [31:0] y);
assign y = sel ? d1 : d0;
endmodule

My MUX4 Module:

module MUX4(input logic [31:0] d0, d1, d2, d3,
input logic [1:0] sel,
output logic [31:0] y);
assign y = sel[1] ?
(sel[0] ? d3 : d2):
(sel[0] ? d1 : d0);
endmodule

My fulladder module

module fulladder(input logic a, b, cin,
output logic s, cout);
logic p, g;
assign p = a ^ b;
assign g = a & b;
assign s = p ^ cin;
assign cout = g | (p & cin);

endmodule
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  • \$\begingroup\$ Sorry I posted all modules and codes that I used. My wd3 ($display(wd3)) is always X in testbench the whole time. It should be result of my ALU. My ALU module doing sum,sub,add and or operation according to ALU_control. I added a design of my project (Figure_1). \$\endgroup\$
    – Jekolaw
    May 28, 2023 at 11:47

1 Answer 1

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In the fileRegisterTB module, you declare the wd3 signal, but you did not connect it to anything. Since you declared it as a logic type, it defaults to the unknown value (X).

You need to connect it to something. The fileRegister module has no output ports. All design modules should have output ports. I see a signal named WD3 in that module; perhaps you meant that to be an output port. Top-level testbench modules are the only modules that don't need ports.

To debug Verilog simulations, using $display alone is usually insufficient. You should also dump a waveform database and view internal signals in a waveform viewer.

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