Buck Converter Compensation and Transient Response

I am trying to compensate a buck converter. I've set up an averaged model of a buck converter in LTSpice.

Here is a picture of the simulation. The B3 voltage takes into account the gain from using a 5 Vpp sawtooth wave for the comparator:

Note: L1 inductor has 210 mΩ series resistance. C1 has a 10 mΩ ESR. Inductor and capacitor values calculated @ 1 MHz operating frequency.

I have closed the loop at ~40 kHz with a target phase margin of 75 degrees. Here is a capture of the bode plot:

When applying an input voltage transient from 0-10 V on the input, the output voltage has some overshoot. With a phase margin of 75 degrees I would not expect the output to be overshooting as much as it is. I'm curious if there is something wrong with my simulation or the op amp itself? Note: V(n001) refers to the output voltage.

Input voltage step simulation capture:

• Once you have the averaged model working, it is advised to implement the cycle-by-cycle version with realistic components and circuitry. As pointed by Andy, most ICs include a soft-start and limit overshoot. Another option, also pointed by Andy, is to force loop closure at power up by soft-starting the reference voltage on the op-amp (see APEC 2015). If well done, the output voltage rises monotonically and the overshoot disappears. With a 40-kHz crossover, check the prop. time of the PWM comparator also. Commented May 29, 2023 at 11:57

When applying an input voltage transient from 0V-10V on the input, the output voltage has some overshoot.

This will happen without extra added sophistication in your circuit such as "soft starting". This is most easily achieved by allowing the reference voltage (2.5 volts) to ramp up during the first few hundred switching cycles. Just allow the 2.5 volts to develop across a capacitor fed via a soft-start resistor and make sure that the 2.5 volts is "activated" only when the input voltage is above a certain valued.

This latter part is called an under-voltage lock-out feature and, prevents the buck regulator from operating when the input voltage is too low.

All these features are on decent buck controllers.

You're employing pole-zero cancellation, given that R4+C2 and R3+C4 have the same time constant as L1+C1. But you can only create real zeroes this way, leaving the gain peak and phase shift of the complex pole pair. So the asymptotic response is correct, you've achieved that (i.e. you can more or less draw a straight line across the loop gain), but you can't cancel out the ringing from the LC.

Note that, because the reference input is noninverting, you will get a different step response that way (which will be similar to the input step response). That wasn't the question, but it seems a likely follow-up question.

The only ways to get rid of the overshoot are:

1. Don't worry about it, it happens. This might be an acceptable solution say for a class D amp.
2. Filter all inputs and outputs such that it can't be excited. You still have the complex-pole-pair, repeated-real-zero response in there, but other poles dominate the response so you don't care.
3. Dampen the LC filter better (set C1 ESR to 3.5Ω, or add >25μF in parallel with same), to reduce its overshoot. Basically, the controller isn't doing anything about this (and can't, it doesn't have enough gain or phase margin to do that).
4. Separate the poles: use two loops and compensate them independently. That is: use current mode control. This is the preferred solution for power supplies, as it intrinsically limits switch current.