FPGAs have among the largest packages and the most voltage rails. This is especially true of the high end devices e.g Stratix, Virtex Ultrascale+ e.t.c. This means a whole lot of decoupling capacitors. Decoupling capacitors is one way to improve the power delivery network and this is very important. Problems with power integrity can actually manifest as problems with signal integrity due to ground bounce.

How does a person know how much decoupling capacitors to use for an FPGA design and their values? Is this an exact science science that must be acquired like with the knowledge of signal integrity, or does it rely only on datasheet and/or outputs from the FPGA design tool (Quartus, Vivado, Libero e.t.c)?

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    \$\begingroup\$ Usually the vendor tells you. \$\endgroup\$ Commented May 29, 2023 at 19:16
  • \$\begingroup\$ If we know what values to use and how many of them to use, what is difficult in designing the PDN? I mean that is all there is to it right? Also, do you they give value and quantity or also some other attribute like ESR, material (ceramic, tantalum e.t.c.)? \$\endgroup\$
    – quantum231
    Commented May 29, 2023 at 19:35
  • \$\begingroup\$ Although its not directly related to the subject, the number voltage rails on the bigger FPGAs are just terrifying. \$\endgroup\$
    – quantum231
    Commented May 29, 2023 at 21:09
  • \$\begingroup\$ The dat sheet will usually have specific recommendations. There may also be a reference design from the vendor that gives an actual example. \$\endgroup\$ Commented May 29, 2023 at 22:18

1 Answer 1


It's not an exact science - usually you get an estimate how your design will consume energy in an FPGA and some margin is added and that's what you need to provide.

Later you ask what's the difficulty.

The FPGA will consume current at the operating frequency, which is high, and the difficult thing is to provide enough capacitance so that the voltage does not have too much ripple when the FPGA gulps current.

The problem is, neither the capacitors or the PCB are ideal. The PCB wiring will have resistance and inductance. Resistance will limit how much instantaneous current is available, and inductance will limit how quickly you can get it. Capacitors themselves have internal ESR and ESL. And depending on dielectric type, a 100nF capacitor may have much less than 100nF of capacitance under the DC voltage bias.

So the difficulty is that you need to provide a power delivery network with low enough impedance at the range of required frequencies. That takes multiple capacitors with multiple capacitances and package sizes to have an effective PDN with low enough impedance at wide frequency range.

Small size and capacitance low-ESL caps near power pins for highest frequencies, slightly larger size with slightly larger capacitance further away for slightly lower frequencies, and the most largest size with largest capacitance the furthest away for the lowest frequencies.

  • \$\begingroup\$ What problems does ESL and ESR create? I guess both of them depend on the package size of the capacitor but am not sure about other details. \$\endgroup\$
    – quantum231
    Commented May 29, 2023 at 20:34
  • \$\begingroup\$ Like I said, ESR causes voltage drop so it limits maximum current, and ESL causes voltage drop because it limits low long it takes before requested current is available. \$\endgroup\$
    – Justme
    Commented May 29, 2023 at 20:36
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    \$\begingroup\$ so if we have put in these decoupling capacitors according to vendor datasheet, do we still need to run some sort of simulation to ensure that the power integrity is preserved? \$\endgroup\$
    – quantum231
    Commented May 29, 2023 at 21:03
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    \$\begingroup\$ @quantum231 You shouldn't need to if your layout is reasonable. But if you are costing cutting you would run the board through a simulation to see exactly how few capacitors you can get away with. \$\endgroup\$
    – DKNguyen
    Commented May 29, 2023 at 21:39
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    \$\begingroup\$ @quantum231 typically not, because directly below the FPGA both planes will be as holey as Swiss cheese - there's signals to be brought out. \$\endgroup\$ Commented May 29, 2023 at 23:20

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