# How do I create a 8-bit binary digit out of the combination two 7-bit ASCII values?

I am implementing a circuit that takes two ASCII values that are in the range 0x30 - 0x39[0 - 9] for the tens digit and ones digit, and then combine them, and output a proper 8-bit binary value reflecting this. D1 is the ten's place digit, D0 is the one's place digit

For example: D1 = 0x311, D0 = 0x32[2]. This means the number is 12, so the output would be 00001100. I have been able to implement this by taking D1 and D0, turning those into binary values, and then using complicated logic to combine them into the respective number. So the output can be any value 0 - 99.

It takes a staggeringly large amount of gates. See below. At this point I'm wondering if it is more efficient to just directly compare the ASCII values and use a chain of AND gates(also inefficient). Does anyone have advice for doing this more efficiently? Also, I don't want to use any components that are analog in some way.

• Basically, you are taking the ten's digit binary value, multiply it by 10 (b1010) and add to the ones digit bits. Bits 0 and 7 are trivial, "the middle bits" anything but. There are many ways to implement such, I think your 2+ level gate implementation looks good to go. For one implementation for multiple digits without a huge multiplier look at reverse double dabble. May 31, 2023 at 4:37
• How do you plan to implement this physically? Discrete logic? CPLD? FPGA? May 31, 2023 at 4:37
• Oh, this is digitally. I'm not exactly sure how to add a digital logic tag May 31, 2023 at 5:07
• (All of the alternatives listed by The Photon are for digital circuits. In addition/as an alternative to tag logic-gates the is digital-logic. Have a look at SN74S484 datasheets to see how it was done with smallish lookup tables ((P)ROMs).) May 31, 2023 at 5:22
• So my implementation isn't less efficient than creating/using a multiplier circuit? May 31, 2023 at 5:33