# What is the highest practical bandwidth of a linear voltage regulator/LDO?

I am trying to evaluate what the highest pratical bandwidth of linear regulator/LDO is. To be more precise, I am looking the bandwidth of the transfer function Vout/Vin.

I think the bandwidth is set by the error amplifier, so it seems that the bandwidth is limited around 100 kHz.

Do you think 100 kHz is the maximum currently achievable? If yes, why can't it be higher? Is it possible to achieve 500 kHz for example or 1 MHz?

• you first need to define 'a voltage regulator'. Is a wide bandwidth powerful output amplifier possible? Of course. Would such a beast find a successful market segment as a voltage regulator? Probably not. This is a marketing, naming, question, not an engineering question. Commented May 31, 2023 at 5:42
• @Neil_UK, Thank you for your comment. I am not looking for a reference. It is more a question about what are the limits and how to explain the limits.
– Jess
Commented May 31, 2023 at 5:52

To get low power supply impedance at high frequency, we add decoupling capacitors on the output of the regulator. So the big difference between an opamp and a regulator is that pretty much all regulators are designed to work with capacitance on the output, whereas opamps designed to drive capacitive loads are rare.

Output caps limit regulator's bandwidth in several ways:

• Since the cap does the job at high frequency, the regulator doesn't need to, so there is no need to pay extra for a very fast error amplifier.

• The crossover between the regulator and the cap needs to be well behaved

The output impedance of the LDO is in parallel with the impedance of the cap. An intuitive manner to judge stability when two impedances are paralleled is that the angle at which the curves intersect on a bode plot should be less than 90°. For example when an inductive impedance crosses over to a resistive impedance, there is no ringing and the curves intersect with an angle of 45°. When an inductive impedance crosses over to a capacitive impedance, there is ringing and the curves intersect with an angle near 90°.

So if the LDO is designed to run with low ESR ceramic caps, the ideal frequency for the first pole (P1 on the plot) shouldn't be too low, in order to ensure the LDO's output impedance is still mostly resistive when it crosses over to the cap. Then the cap dominates the output at high frequency, and the next pole P2 is hidden and doesn't matter for stability.

Now consider the blue curve:

If the error amplifier is too fast, the LDO will remain in control of the output at a frequency where the capacitor becomes inductive. Since what matters here is LDO bandwidth versus capacitor inductance, this can also happen if the LDO isn't particularly fast but there is no cap at the LDO output, and a very long trace or wire between the output of the LDO and the cap near the load, adding a lot of inductance. In this case, if the output impedance of the LDO is lower than the cap's impedance, then the cap no longer dominates the output at high frequency, and it no longer hides the second pole P2. That makes the system unstable.

With common caps values and types, the output impedance crossover between the LDO and the cap will occur somewhere between 100kHz and 1MHz, and the cap will dominate output impedance above 1MHz. So it is not necessary to have a higher bandwidth than this in the LDO.

• Thank you for your answer ! :) So this is only the output impedance which limit the bandwidth of a linear voltage regulator ? Is it always the case ? I mean generally when I tried to study the stability of a system, I try to extract the bode plot and then I try to compensate this system to make it stable. But I do not ask my self about the effect of output impedance... This analysis seems a great point of view
– Jess
Commented May 31, 2023 at 10:05
• Output impedance is a way to look at it "intuitively" and see what the cap and regulator are doing separately on the plot. You can also use loop gain/phase and the usual stability criteria, in this case the output capacitors should always be included in the simulation, because they are inside the loop. Commented May 31, 2023 at 10:43