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All sketches of JFET construction that provide an actual 3D impression suggest that the channel is buried, e.g. here.

enter image description here

I imagine that the formation of such a channel geometry requires at least two implantation steps. Assuming n-channel in a p-substrate:

  • Either a deep n-well with a smaller p-bar above it
  • Or a deep long buried n-tube and a second n-type implantation to form the connections from the buried n-tube to the surface.

Wouldn't it be possible to just form a long shallow n-region at the surface using a single implantation and then connect one end as source and the opposite end as drain? The depletion would form only from the bottom, but it should work as a JFET regardless, no?

Low skill paint sketch:

enter image description here

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  • \$\begingroup\$ The lightly doped channel needs to pinch, doesn't it? The gate material is very highly doped so it's a good conductor and there's no need for aluminum to connect the gate material below to the gate material on top if they simply connect on the sides as shown in your first diagram. I guess I'm not sure why you think it would work well as you describe in the bottom diagram. But maybe I can't interpret it as you intended it? \$\endgroup\$ Jun 1, 2023 at 8:12
  • \$\begingroup\$ @periblepsis I thought that the gate doesn't need to be very conductive. I thought connecting it anywhere will essentially put the entire p-area at the same potential as no current is flowing in the p-zone. As this p-zone (the gate) is driven more negative, the depletion zone under the n-channel would grow and push "up" until it reaches the surface, at which point the channel is pinched off. That is my thinking. \$\endgroup\$
    – tobalt
    Jun 1, 2023 at 8:27
  • \$\begingroup\$ From Solid State Electronic Devices, 7th Edition, Ben G. Streetman & Sanjay K. Banerjee, page 261, "Since the conductivity of the heavily doped p+ regions is high, we can assume that the potential is uniform throughout each gate." (The example uses p+ for the gate material.) Let me post a picture. Here's another. And another. \$\endgroup\$ Jun 1, 2023 at 8:31
  • \$\begingroup\$ They also write on the same page, "It is common practice to connect the two gate regions electrically". \$\endgroup\$ Jun 1, 2023 at 8:36
  • \$\begingroup\$ @periblepsis I have seen such explanations. And I am wondering why that has to be done (let's assume for low frequency operation for now). Wouldn't the whole p substrate just assume the gate potential with no current flowing in it ? \$\endgroup\$
    – tobalt
    Jun 1, 2023 at 8:43

1 Answer 1

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A Premise. The physical realization of the device must follow as closely as possible the structure identified by mathematical model behind it. Otherwise, second order effects which are considered to be negligible may prompt out with unexpected/undesirable results.

Said that I can proceed and answer the question(s).

Q. Wouldn't it be possible to just form a long shallow \$n\$-region at the surface using a single implantation and then connect one end as source and the opposite end as drain?

A. As it is noted in the OP, (junction) field effect structures of this type are constructively (or better intrinsically, meaning that you cannot get rid of them) present in any field effect device, their control pin being called the bulk B: see for example this Q&A on how this terminal is connected in field effect devices. Moreover, this structure works exactly as an expected, provided the gate and other terminals are properly biased, but there are several reasons which prevent semiconductor technologist to produce JFET devices in that form: possibly the most important are listed below.

  1. The bulk region is lightly doped respect to the channel one, and this means that the junction depletion layer extends more inside such type of gate than in the channel of the device. This means that controlling channel conduction by reducing/enhancing its width requires larger voltage variations respect to a structure where the gate has a higher doping respect to the channel, and this means lower forward transconductance \$g_m\$ an thus lower gain. Thus even if the geometry is (almost) the same, you get a worser JFET device.

  2. Due to the same low doping, the bulk gate ha constructively a non negligible series gate extrinsic resistance \$r_G\$. From the equivalent circuit point of view, the result is the one shown below.
    From this it can be inferred that this resistance has two bad effects on the overall device performance. First, it rises the gate equivalent noise voltage in the following way
    $$ e_{n_\text{tot}}=\sqrt{e_{n_i}^2+e_{n_{r_G}}^2}, $$ and second it creates a high frequency pole that limits the high frequency response of the JFET. Again, you get a worser JFET device.

schematic

simulate this circuit – Schematic created using CircuitLab

  1. The gate area \$A_G\$ affects with inverse proportionality the gate flicker (\$1/f\$) intensity noise voltage \$e_{1/f}\$: if you give up the top diffused gate, you get a device with lower gate area and thus higher flicker/burst noise. In sum, you get again a worser JFET device.

Q. The depletion would form only from the bottom, but it should work as a JFET regardless, no?

A. Yes and no. As said above, a single diffuse structure works as a JFET device provided its bulk contact is operated as a gate electrode. Nevertheless, leaving the upper side of the channel without a properly biased gate region causes a subtle problem due to the fact that the surface of the device cannot be leaved as is (or more correctly said, will not rest a simple semiconductor surface).
The device must be protected from chemical contaminants, thus it is necessary to build a \$\mathrm{SiO_2}\$ passivating layer on the top of the wafer, and when there isn't a gate region below this layer causes at least two different problems
The first one is a higher leakage current of the JFET channel, since the structure is now a JFET connected in parallel with a MOSFET without a proper gate bias (effectively without a gate). This situation is well described in the following picture (taken from the third printing of the High Speed Transistor Switching Handbook, edited by William D. Roher, Motorola 1963), which shows this effect and a countermeasure for a planar PNP BJT. enter image description here The second one is the classical SOI floating body effect, that causes a serious distortion of the device characteristics as shown by the orange and violet lines in this picture. In turn, you get again a worser JFET device.

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    \$\begingroup\$ I know such comments are discouraged, but I want to thank you for your time composing this detailed, comprehensive and very clear answer. \$\endgroup\$
    – tobalt
    Jun 8, 2023 at 10:56
  • \$\begingroup\$ @tobalt thank you for your kind words. I am glad to be of some help. \$\endgroup\$ Jun 8, 2023 at 12:04

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