The output voltage level of the TTL logic family is from 0 to 0.4 volts (LOW) or 2.4 to 5 volts (HIGH). Suppose we have a TTL inverter with a square wave of 5 volt amplitude as input (0 volt and 5 volt). What will be the voltage levels at the output? On what factors will the output voltage levels depend?
The output voltage of a TTL gate will depend entirely on what's connected to it, how it is "loaded".
In fact, the output voltage of anything will depend on the load. It's just that TTL logic outputs are notoriously "weak", having resistance that seriously limits the current they are able to source and sink into/out of any connected load.
To complicate matters, their outputs are far better at sinking current (from a higher potential), than sourcing (to a lower potential). In other words, they are better at "pulling down" (where current is drawn into the output, from a higher potential) than "pulling up" (in which case current is leaving the output, flowing to a lower potential). For example, it's generally OK to connect an LED between a TTL output and +5V (below left), but not to ground (right):
It's not easy to say what the output voltage will be; everything depends on the load, and whether that load is a current source or sink, from the perspective of the gate itself.
In general, for an output to be called "TTL compatible", it must comply with a certain set of extreme-case requirements. For example, it must be able to source a certain amount of current, while maintaining a "high" output of at least +2.4V. It must also be able to sink a certain amount of current while maintaining a "low" output of at most +0.4V.
The actual output current limits depend on the family of logic ICs. the 74xx series has different specifications from the 74LSxx series, which differs from 74ALSxx, and so on.
Compare this to CMOS devices (like the 74HCxx series), which have much more symmetrical output characteristics (meaning they can source and sink current with similar ease). Their outputs are entirely compatible with TTL, in that they meet (and far exceed) TTL output voltage minima/maxima, but have much better current sourcing ability. That's why you often see LEDs connected between CMOS outputs and ground, something you'd never do with TTL.
It's perfectly possible for you to over-load both TTL and CMOS outputs in some way that renders the gate unable to comply with specified minima and maxima, but that's not the gate's fault.
For these reasons it's not possible to say with any certainty what a TTL gate's output voltage will be. The best we can do is say that as long as the output is connected to a load that doesn't violate the gate's recommended operating conditions, when it's supposed to be high, the output will be +2.4V or greater, and when it's supposed to be low, the output will be +0.4V or less.
For a TTL inverter (such as one of the gates in a 74LS04), this translates to: as long as the output is connected to a load that doesn't violate TTL recommended output loading, then
When its input is less than +0.8V, the output will be +2.4V or greater.
When its input is greater than +2.0V, the output will be +0.4V or less.
These are the only guarantees you get, regarding output voltage.
All we can say for certain is that a logic LOW should be under 0.4 volts, and a HIGH should be above 2.4 volts.
If I recall correctly, in practice, a LOW may be about 0.2 volts, and a HIGH will be 3 - 4 volts when connected to a TTL input.
Both levels will depend on what the output is connected to. If the output is connected to a load passing more than 20 mA, the output voltage (high or low) may not meet the official TTL High or Low voltage levels.
The output voltages are in the range you quoted so you have the answer already.
The output voltages will be guaranteed to be within that specified range, when loaded within the specified load current range, and the chip being powered with supply voltage that is also within the allowed range.
If there is a heavier load than specified, then the voltages may be out of the specified range.
There are different TTL compatible logic families and even within them there are chips with standard outputs and some chips with stronger outputs that can be used as a buffer.
For any specific chip, you need to see the data sheet to know what it is capable of.
It is complicated to explain the detail.
Briefly speaking, traditional 5V TTL gate output stages use two NPN transistors.
The transistor at the bottom is for pulling down (sink current.) We know a saturated NPN Vce can be as low as 0.x voltage. Therefore, the low output is below 0.4V.
The transistor at the top is for pulling up (source current.) We know an NPN needs about 0.6V Vbe to turn on. For some reason, a diode is needed between the top NPN and the output stage, another 0.6V. Therefore, TTL output high is almost impossible to be higher than 5-0.6-0.6 = 3.8V. In a real IC, there is a protection resistor causing more voltage drop.
In my experience, TTL output low is about 0.2V to 0.4V; output high is about 3V to 3.5V.
How do we demystify TTL output stage?
TTL circuits are some of the strangest creations of circuit designers (perhaps rivaled only by ECL circuits). If we type in the Google window "transistor-transistor logic", more than 18 million pages will pop up telling us "this is so..." but we will hardly find any pages that say "why this is exactly so..." We have no choice but to try to answer our own questions.
There are two oddities in these creations - first in their input part and then in their output part. Here, the object of our attention is their output part.
Reinventing TTL output stage
I am not a circuit designer, just a "circuit thinker"... and I can only guess what the designers had in mind in the 60's. What I can do is try to reproduce their train of thought in the form of an imaginary pseudo-invention.
The idea of the complementary output stage
... is extremely simple and intuitive - to change simultaneously and in opposite directions the resistances of a voltage divider. This configuration can be thought of as two cross-fading "pull-up" and "pull-down" resistances.
This idea was implemented in its simplest electromechanical form already in the 19th century as a potentiometer. A unique property of this device is that when we move the wiper, the total resistance, current and voltage remain constant; only the ratio between partial resistances and voltage drops changes...
... and we use one of the voltages (usually the grounded one) as an output voltage Vout. Use DC sweep simulation.
Complementary (push-pull) stage
It was implemented a century later using tubes and transistors. The only difference with the potentiometer is that the resistances are electrically controlled and non-linear.
The most logical solution in our opinion now would be for them to then use different (NPN and PNP) transistors. They should be connected with their collectors (as today MOS transistors in a CMOS pair are connected through their drains). We can name this "complementary TTL" structure CTTL:-)
I will use CircuitLab to explore the schematics below. Since they are conceptual, I propose to drive the transistors in the most straightforward way by applying two separate input voltages (Vin1 referenced to Vcc and Vin2 to ground) directly to their base-emitter junctions. Because this is inconvenient in practice, later we will combine them into a single input voltage Vin. We only want to be careful not to exceed the permissible base-emitter voltage. Let's first manually explore three typical states of this configuration.
Vin = 0 V (Vin1 = 700 mV, Vin2 = 0 V). After carefully setting these input voltages, Q1 will be on and Q2 off. A current flows through Q1, exits and passes through the load (a voltmeter with intentionally reduced to 10 k resistance). So the stage is sourcing.
Vin = 2.5 V (Vin1 = 750 mV, Vin2 = 712 mV). During the transition, both transistors must pass current (the output should not remain "floating") and the output voltage must be equal to half of the supply voltage. Adjust Vin1 and Vin2 carefully to achieve this condition.
Vin = 5 V (Vin1 = 0 V, Vin2 = 700 mV). Now the roles are reversed - Q1 is off and Q2 on. A current flows through the load (a voltmeter with intentionally reduced to 10 k resistance), enters and flows through Q2. The stage is sinking.
Vin = var (Vin1 = 750 mV - 0 V, Vin2 = 0 V - 697 mV). Finally, let's investigate the stage by a linearly varying input voltages to see the transition. Since I have used CSV voltage sources, use time-domain simulation.
As you can see from the graph, the characteristic resembles that of the CMOS stage. It is very steep in the middle because the transistors behave as current sources at the time of switching (dynamic load) and reach the supply rails when they are on. So our "CTTL stage" is almost perfect.
Conceptual phase splitter circuit
It is time to replace the two separate input voltage sources (one of which is connected to Vcc) with just one grounded source Vin. Let's model it first with the ubiquitous voltage divider, only a little more complicated - with two constant resistors R1 and R2 and a variable resistor RQ inserted between them.
When we vary RQ, the common current through the three resistors in series varies (unfortunately non-linearly) and the voltage drops across R1 and R2 vary as well. So if RQ is a voltage-controlled resistor, the two transistor input voltages will be controlled by the single input voltage.
Practical phase splitter
It remains only to replace the variable resistor with a transistor Q that will act as a voltage-controlled "resistor".
Now the voltage drops across R1 and R2 depend almost linearly on the input voltage.
Prototype of TTL output stage
However, for a number of reasons, PNP transistors were inconvenient to use, and so the designers decided to replace Q1 with another NPN transistor... and this is where the trouble starts (note that it works in active mode as an emitter follower, not as a transistor switch). Let's do it and connect the phase splitter to the NPN transistor pair...
... and sweep Vin. But what is this significant current surge at the moment of switching?
Aha... clear! This is the moment when both transistors are "on". We need to somehow reduce the overlap and limit the current surge.
Classic TTL output stage
We notice that when Q is on, only the Q2 base-emitter junction is in parallel to Q1 base-emitter junction and that is not enough to be Q1 off. We need to insert another diode somewhere in the loop. The designers chose to put it in the emitter of Q1 apparently because the current is higher there. Then, to limit the current, let's insert a 130 ohm resistor R3.
Now let's see how the output voltage changes.
At the moment of transition, the current is significantly reduced.
Why the HIGH output voltage is low
A bunch of problems lead to this:
A voltage drop is lost in the resistor R1
Another voltage drop is lost in the resistor R3
0.7 V is lost in the emitter follower Q1
Another 0.7 V is lost in the diode D
You can see it in the graph below.
How to make it high
We can "pull up" the TTL output by another resistor R4 connected to Vcc. The trick is that diode D is off and disconnects Q1 from the output.
As you can see, the output voltage is almost 5 V but only if there is a high resistance load connected.
Your interviewer is probably trying to gauge your experience with different logic types, as well as your level of knowledge about IC input and output structures.
The answer to the TTL output swing question is, it depends on how much current the gate is being asked to source (drive high) or sink (drive low.)
What is that output voltage, then? You can't say exactly, at least without an accurate model of the device. But you can say under what load conditions (sourcing or sinking) the gate can achieve a valid high or low, as these are stated in the datasheet and tested in manufacturing.
Example TTL datasheet: 74LS00 (link)
What are those limits? The 74LS00 datasheet only guarantees:
- When sinking logic-low, Vol will be of no greater than 0.5V at 16mA Ioh
- When sourcing logic-high, Voh will be no less than 2.5V at -0.4mA Ioh
Notice that TTL Ioh is really weak compared to its Iol: just -0.4mA for the stated Voh vs. 16mA for Vol. Why is that? TTL inputs require DC current to pull them down, so a output driving a lot of TTL loads will need much more Iol than it will Ioh. So the TTL output can get by with a weak high drive and save some power.
What makes the output behave that way? TTL devices use an output structure composed of a pull-up resistor, two NPN transistors, and a diode; together called a ‘totem-pole’ output. Totem-pole outputs have limited output swing and weak high drive because of the behavior of these components. But for driving other TTL it's ok, as the TTL loads themselves will be pulling up the output too.
More detail about TTL here: NAND gate problem
And try a simulation here