How can I find the maximum data rate of a voltage level translator IC?

Question

I am planning to use the NVT2010 in my board for voltage level translation of the Ethernet RMII interface.

We know that the speed of RMII interface is 10/100Mbps. After checking the datasheet, I am not able to reach a conclusion that this IC will support RMII speed or not. In the TI voltage level translators datasheet, the data rate is directly given.

How can I find the data rate of this IC?

Answer 1

The NVT2010 does not have a push-pull output driver. The input and output pins are described to be:

• low-voltage side; connect to VREFA through a pull-up resistor.

• high-voltage side; connect to VREFB through a pull-up resistor

Thus, output is open-drain only, and its data rate is highly dependent upon the selected pull-up resistor and load capacitance. This forms an RC circuit with a 10%-90% rise time of ~2.2RC.

Section 12, Performance curves, of the datasheet says,

Maximum data rate is dominated by the system capacitance and pull-up resistors.

Unfortunately, for marketing reason, the summary misleadingly states that:

NVT2008/10 can also be used in applications where a push-pull driver is connected to the data I/Os.

It only says "can be used with push-pull I/O", it doesn't say that it actually has a push-pull I/O.

An example is also given, that,

Bit widths of 8-bit to 10-bit are offered for level translation application with transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a pull-up of 197 Ω

Thus, to support operating at 50 MHz for RMII, due to its open-drain output, I think it requires a rather small pull-up resistor value. The idle current and power consumption will be a bit high (but it's all relative). A level translation with push-pull output would certainly be easier to design with and runs at lower power. Perhaps you can find a push-pull one and save yourself from the headaches.

But an open-drain translation can be made to work with a small pull-up resistor value and load capacitance.

Calculation

The datasheet contains detailed instructions on selecting resistor values, see the datasheet 7.5. How to design for maximum frequency operation.

The maximum operating frequency is determined by:

$$ f_{\text{max}} = \frac{1}{t_{\text{high(min)}} + t_{\text{low(min)}} + t_r + t_f} $$

where,

• \$ t_r \$ is the signal rise time
• \$ t_f \$ is the signal fall time
• \$ t_{\text{high(min)}} \$ is the minimum time the signal stays at the HIGH level (excluding rise time)
• \$ t_{\text{low(min)}} \$ is the minimum time the signal stays at the LOW level (excluding fall time)

And to determine the signal rise and fall time, we to select a pull-up resistor value R based on the input capacitance of the Ethernet PHY chip. This is usually documented in the Electrical Specification section of the datasheet, often 10 pF, but make sure to check your datasheet. To allow circuit board parasitic capacitance, perhaps we need to add another 3 pF to 5 pF.

For a ballpark calculation, we assume the input capacitance is 15 pF, and we select a 100 Ω pull-up resistor (but do note that the current limit of the level translator is 15 mA, depending on your supply voltage, 100 Ω may be too low).

So it's 10%-90% rise time of the level translator is:

$$ 2.2\text{ RC} = 15\text{ pF} \times 100\text{ } \Omega = 1.5\text{ ns} $$

For RMII, I assume the signal is 50 MHz and its period is 20 ns. So it's roughly 10 ns HIGH in total and 10 ns LOW in total, including rise and fall time. The RMII spec also says,

7.4.3 Rise and Fall Time: Output waveforms shall have a rise and fall time between 1 and 5 ns. This shall be measured between the points on the waveform which cross 0.8V and 2.0V.

So again, for a ballpark calculation, I assume the rise time is only a small fraction of its high time, such as 1/5, then the allowed rise time of RGII is:

$$ 10\text{ ns} \times 20\% = 2.0\text{ ns} $$

Don't take my words for it, it's only a quick ballpark calculation and I didn't check it in detail. But I think it will probably work.