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I have one FPGA (Artix-7 XC7A100T-2CSG324C) connected by a PCB trace to another FPGA (Artix-7 XC7A100T-2CSG324C.)

The PCB trace is 3.4 meters long, 0.154mm wide, 0.185mm high from GND plane. The dielectric between signal and ground planes has Dk=3.6 and height of 0.15mm, and a 0.035mm trace height.

This signal is on its own separate layer. Above is a power plane and below is a ground plane. On the same layer, there are ~4 other signals similar to the one discussed here. Additionally, there is a LVDS signal (1 MHz) that is separated from these signals by a GND infill on the same layer.

I want to know if I switch the FPGA output to a HIGH (3.3V), would the other FPGA be able to see the HIGH (3.3V)? In the end, I am looking at something around 9600 bits per second, but if I can operate at a faster frequency then I won't be upset.

Initially thinking through this problem, I imagine that the PCB trace is too long for the HIGH to be seen, so I want to know the best way to make that HIGH seen. I have been looking around and I have seen people talk about buffers. I don't know how to select a buffer and what information is needed when selecting a buffer for this application.

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  • \$\begingroup\$ What frequency or data rate are you trying to achieve? \$\endgroup\$ Commented Jun 2, 2023 at 22:06
  • \$\begingroup\$ @TomCarpenter I don't really have a data rate in mind. I would say 9600 bits per second. However, if it can go faster then that would be preferred. \$\endgroup\$
    – trident_
    Commented Jun 2, 2023 at 22:26
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    \$\begingroup\$ You have a single PCB that's 3.4 meters? (I realize that with doubling back, the trace can be somewhat longer than the PCB size, but generally not by a factor of 10) \$\endgroup\$
    – Ben Voigt
    Commented Jun 2, 2023 at 22:35
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    \$\begingroup\$ Let me ask you (OP) this. Why do you think that a PCB trace is too long for the HIGH to be seen? \$\endgroup\$
    – SteveSh
    Commented Jun 3, 2023 at 0:20
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    \$\begingroup\$ You (OP) have a single PCB that is 3.4 meters long? \$\endgroup\$
    – SteveSh
    Commented Jun 5, 2023 at 15:00

1 Answer 1

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If you do want to use buffers, get two 3.3V CMOS inverter gates and put them at 1 and 2 meter points from the receiving FPGA (so 2.4 and 1.4 meters from the transmitter). Inverters are simpler and faster gates than non-inverting buffers, and any even number will cancel out the inversion.

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