Do we decide the output of a sequental circuit based on its present state or next state?

Question

Suppose in a sequential circuit, we have an output which is based on the present state and the input, and the input of flip flops are based on the given input. When we change the input the output will change. Also the FF state will change from present state to the next state. And then the output of the circuit may change as well.

Based on which state do we decide the output?

For instance let's say we have a circuit like this (sorry I forget the clock input):

Assume that our present state is A=1, A'=0.
Let's say we give 1 as x input. Then the output y will change to 1 and after that the FF state will change to A=1, A'=0. So the output will change again, this time to 0.

Which output is correct?

Answer 1

When [input x changes also] the FF state will change

no, not when A is a flip flop. State will be replaced as a consequence of clock signal changes - by the same state, or a different one.

Based on which state do we decide the output?

There is just one state at any one time. There may be signals at the inputs of storage elements determining in conjunction with the clock signal what the one and only state will be next.

A=1, A'=0. Let's say we give 1 as x input. Then the output y will change to 1.

I beg to differ: I see an EXOR with both inputs 1, y should be 0.

after that the FF state will change to A=1, A'=0. So the output will change again, this time to 01.
Which output is correct?

The FF state A will change to 1 following the appropriate change in the clock signal: there is a 1 at input D.
Both output signals are correct: They belong to different machine states.

A (finite state) machine with outputs depending asynchronously on inputs has been formalised as a Mealy machine.
A machine with outputs depending on state, only is a Moore machine(, too).
For "best synchronicity", each output is a register output - no intervening circuitry.
To muddle things, state machines can be realised with "transparent latches", latch output depending on input at one clock level, independent of input at the other clock level.

Answer 2

If I'm understanding you correctly, I think the answer is "you wouldn't design the circuit this way". You would want to design the circuit so that each clock cycle has at most one input change, at most one state transition, and at most one output change. (Obviously the input could change multiple times, depending on where it's coming from; but usually all but one input per clock cycle would be ignored.)

If you have a circuit where an input change can cause a temporary output change, due to circuit delays, but eventually the output settles down to a different value: that's called a "glitch", and it's considered undesirable. That terminology usually applies to combinatorial (that is, non-clocked) logic circuits.

In a clocked logic circuit, you would normally design it so that your output only changes in sync with the clock signal -- at most once per clock cycle, and always at the same time during the cycle. A clocked logic circuit like this wouldn't normally be designed to let the output change immediately when the input changes, regardless of the clock signal. As you have observed, doing that makes the circuit hard to reason about.

Answer 3

The answer depends on what is in the block labeled "A".

If that's a clocked flip flop of some sort, then you're missing the clock input for it. And the ouputs of that block will not change until the proper clock edge is received. And that would make it a Mealy machine.

If that block is just combinatorial logic (ANDs, NOTs, NANDs, etc), then you have a feedback loop and the output may oscillate at a rate determined by the prop time through the gates. Or it could latch, like an asynchronous SR flip flop.