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Suppose in a sequential circuit, we have an output which is based on the present state and the input, and the input of flip flops are based on the given input. When we change the input the output will change. Also the FF state will change from present state to the next state. And then the output of the circuit may change as well.

Based on which state do we decide the output?

For instance let's say we have a circuit like this (sorry I forget the clock input): minimal finite state machine

Assume that our present state is A=1, A'=0.
Let's say we give 1 as x input. Then the output y will change to 1 and after that the FF state will change to A=1, A'=0. So the output will change again, this time to 0.

Which output is correct?

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  • \$\begingroup\$ Confusing to me. Note that \$x\$ can vary asynchronously to the clock and the state of the DFF. So \$y\$ is based upon a synchronous state (of the DFF) and an asynchronous input. What are you really asking about? Perhaps someone else can see more clearly. But skimming this I'm not sure what you need to hear. \$\endgroup\$ Jun 4, 2023 at 11:26
  • \$\begingroup\$ In your circuit, the output depends on the present state (A) and the input X. That makes it a Mealy machine. \$\endgroup\$
    – SteveSh
    Jun 4, 2023 at 11:27
  • \$\begingroup\$ @periblepsis i cant underestand how the output will get determined. for example in the condition i described below the image. \$\endgroup\$
    – Emz
    Jun 4, 2023 at 11:43
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    \$\begingroup\$ There is a possibility Y will glitch. The output depends on how input X changes in relation to the clock. \$\endgroup\$
    – Kartman
    Jun 4, 2023 at 12:48

3 Answers 3

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When [input x changes also] the FF state will change

no, not when A is a flip flop. State will be replaced as a consequence of clock signal changes - by the same state, or a different one.

Based on which state do we decide the output?

There is just one state at any one time. There may be signals at the inputs of storage elements determining in conjunction with the clock signal what the one and only state will be next.

A=1, A'=0. Let's say we give 1 as x input. Then the output y will change to 1.

I beg to differ: I see an EXOR with both inputs 1, y should be 0.

after that the FF state will change to A=1, A'=0. So the output will change again, this time to 01.
Which output is correct?

The FF state A will change to 1 following the appropriate change in the clock signal: there is a 1 at input D.
Both output signals are correct: They belong to different machine states.

A (finite state) machine with outputs depending asynchronously on inputs has been formalised as a Mealy machine.
A machine with outputs depending on state, only is a Moore machine(, too).
For "best synchronicity", each output is a register output - no intervening circuitry.
To muddle things, state machines can be realised with "transparent latches", latch output depending on input at one clock level, independent of input at the other clock level.

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  • \$\begingroup\$ I think you've glossed over the fact that the output can change without the application of the clock, though you did sort of hint at that in your last paragraph. \$\endgroup\$
    – SteveSh
    Jun 4, 2023 at 20:44
  • \$\begingroup\$ @SteveSh Should one reason about inputs the question doesn't mention? The explicit question is based on its present state or next state? \$\endgroup\$
    – greybeard
    Jun 4, 2023 at 21:31
  • \$\begingroup\$ The diagram supplied as part of the question does have an input that directly relates to the output. Also, there is nothing in the question about a clock being involved. An asynchronous state machine does not need a clock. Just saying you've made some assumptions in your answer about "A" that OP does not state in the question. \$\endgroup\$
    – SteveSh
    Jun 4, 2023 at 23:56
  • \$\begingroup\$ @SteveSh nothing in the question about a clock being involved I read sorry I forget the clock input. \$\endgroup\$
    – greybeard
    Jun 5, 2023 at 0:34
  • \$\begingroup\$ OK. If that was in the original post, I missed it. OP should have annotated his sketch to reflect that aspect of the circuit. \$\endgroup\$
    – SteveSh
    Jun 5, 2023 at 11:54
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If I'm understanding you correctly, I think the answer is "you wouldn't design the circuit this way". You would want to design the circuit so that each clock cycle has at most one input change, at most one state transition, and at most one output change. (Obviously the input could change multiple times, depending on where it's coming from; but usually all but one input per clock cycle would be ignored.)

If you have a circuit where an input change can cause a temporary output change, due to circuit delays, but eventually the output settles down to a different value: that's called a "glitch", and it's considered undesirable. That terminology usually applies to combinatorial (that is, non-clocked) logic circuits.

In a clocked logic circuit, you would normally design it so that your output only changes in sync with the clock signal -- at most once per clock cycle, and always at the same time during the cycle. A clocked logic circuit like this wouldn't normally be designed to let the output change immediately when the input changes, regardless of the clock signal. As you have observed, doing that makes the circuit hard to reason about.

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The answer depends on what is in the block labeled "A".

If that's a clocked flip flop of some sort, then you're missing the clock input for it. And the ouputs of that block will not change until the proper clock edge is received. And that would make it a Mealy machine.

If that block is just combinatorial logic (ANDs, NOTs, NANDs, etc), then you have a feedback loop and the output may oscillate at a rate determined by the prop time through the gates. Or it could latch, like an asynchronous SR flip flop.

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