I am trying to understand metastability as introduced in the Technion IEEE paper (link). But I am struggling a little with some of the concepts, and wanted to ask about that.
Question: They mention that when the input D to the FF changes right as CLK2 is turning high, it can introduce metastability in the master latch. They present the following graph by playing around with the relative timing about D and CLK2 to show how metastability is introduced in the circuit.
Caption under the image: Empirical circuit simulations of entering metastability in the master latch of Figure 2 (left). Charts show multiple inputs D, internal clock (CLK2) and multiple corresponding outputs Q (voltage vs. time). The input edge is moved in steps of 100ps, 1ps and 0.1fs in the top, middle and bottom charts, respectively.
I do not understand why moving the input edge by different time steps produces such varied plots. The relative input - clock timings are the same, only the time steps are varied. Why does it take the circuit so long to stabilize in the 3rd case compared to the first?
I looked at the literature references they mentioned, and also in my notes, Wiki, university lectures on metastability but to no avail.