I am laying out a PCB containing an Ethernet connector with integral magnetics, and a Micrel KSZ8051MNL Phy. This is for a 100mbps application.

In an attempt to reduce EMI, and make the Ethernet data tracks as perfectly balanced as possible, and to match their lengths as closely as possible, I have ended up routing them in quite a curvy way.

Question 1: Is it worth going to this effort for such short tracks? The trivial way to lay out these tracks would have resulted in a difference of about 1.7mm.

Question 2: Is there any downside to this almost 360º loop?

(BTW, the Phy has integral terminators, which is why they don't appear on the PCB.)

Differential tracks

  • \$\begingroup\$ Have you considered rotating the Phy counterclockwise? Also, is this all going underneath the ethernet jack - are those its mounting holes? \$\endgroup\$
    – pjc50
    Apr 25, 2013 at 15:17
  • \$\begingroup\$ @pjc50 - I have tried rotating the Phy 90º anticlockwise, but it causes other problems in the layout. This seems to be the least worst option. This is all underneath the Ethernet connector. Those are its mounting holes, shield pins and LED pins. \$\endgroup\$ Apr 25, 2013 at 15:21
  • 2
    \$\begingroup\$ Everything else aside, those are some sexy traces! \$\endgroup\$ Apr 25, 2013 at 21:17

2 Answers 2


Consider this: According to the Ethernet spec, a standard Ethernet connection is allowed to go through up to 100 meters of cable, including several patch cables, patch panels, etc.

Then look at your PCB and try to imagine how your trace matching will influence the signal integrity given the overall Ethernet connection scheme (cables, patch bays, etc.). It is unlikely that anything you do in 1-2 inches of trace length will be as bad as a typical patch panel or wall jack.

But... The better you route your signals on your PCB, the easier it will be for you to meet EMI regulations. It is impossible for me to say how much easier it will be, but it will be easier.

My general rule is this: Route the traces as best as you can, but within reason. Run them as differential pairs, but don't worry too much about matching trace lengths exactly. Take care of them, but don't stress over it either.

I have done this on many Gig-E boards and have never had issues.

  • \$\begingroup\$ OK, thanks. And there's no problem with the loop round that pin? \$\endgroup\$ Apr 25, 2013 at 15:11
  • \$\begingroup\$ @Rocketmagnet The loop around the pin is fine. I forget if Ethernet (or that chip) supports reversed polarity eithernet signals. If it does, you can just swap the signals on the connector and get rid of the looped signal routing. But if not, it is still fine. \$\endgroup\$
    – user3624
    Apr 25, 2013 at 15:21

I would say that that level of trace length matching is way overkill.

However, I would be somewhat concerned about how close the one trace is to the large hole in the lower-left quadrant. The stray capacitance from this could unbalance the pair — probably not seriously in this instance, but in general, you should try to keep other traces away from a balanced pair by 2-3× the pair spacing.

  • \$\begingroup\$ Thanks for the quick answer. I'm also worried about that hole. I should have mentioned it in my question actually. Problem is I'm stuck between a rock and a via. I can't move the tracks away from the hole without moving them closer to the other pair. \$\endgroup\$ Apr 25, 2013 at 15:01
  • \$\begingroup\$ Yes, when you are stuck for space, you should at least try to divide it evenly on both sides of the balanced pair. \$\endgroup\$
    – Dave Tweed
    Apr 25, 2013 at 15:05

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