In the 1-bit ALU and the table that is shown below, as you can see, the output is -1 when F0 = 1, F1 = 1, ENA = 0, ENB = 0, INVA = 1, INC = 0. The table is taken from a book (Structured Computer Organization Book by Andrew S. Tanenbaum, Chapter 4, Section 4.1, Figure 4.2). The diagram is from Figure 3-18 in the book. Sadly, this was not explained anywhere.
I am well aware of the fact that when F0 and F1 are both 1, addition is going to take place between A and B. As ENA and ENB are both zeroes, we are basically zeroing the AND gates with A. For what I know, INVA complements the value of A if it is set, that is, I am going to get a 0 if A is 1 and 1 if A is 0.
How are we landing to a -1 output from these?