# How do we get a -1 in a 1-bit ALU?

In the 1-bit ALU and the table that is shown below, as you can see, the output is -1 when F0 = 1, F1 = 1, ENA = 0, ENB = 0, INVA = 1, INC = 0. The table is taken from a book (Structured Computer Organization Book by Andrew S. Tanenbaum, Chapter 4, Section 4.1, Figure 4.2). The diagram is from Figure 3-18 in the book. Sadly, this was not explained anywhere.

I am well aware of the fact that when F0 and F1 are both 1, addition is going to take place between A and B. As ENA and ENB are both zeroes, we are basically zeroing the AND gates with A. For what I know, INVA complements the value of A if it is set, that is, I am going to get a 0 if A is 1 and 1 if A is 0.

How are we landing to a -1 output from these?

The top diagram represents a 1-bit slice of an N-bit ALU, as shown in Figure 3-18. Figure 3-19 shows an example diagram of an 8-bit ALU, where 8 of the 1-bit blocks are connected together.

Figure 4-2 assumes that you have more than 1 bit, for example an 8-bit ALU. The bottom row in the table is -1, which we can infer from the text, is a 2's-complement value. -1 means that the output of each of the 8 ALU bits is 1. In Figure 3-19, this means that O0=1, O1=1, ..., O7=1.

Fig. 3-19 also shows that Carry in of the 1st ALU bit is connected to INC, which from the last row in the table is 0. The combination of the other inputs forces Carry out of each ALU bit to follow Carry in. This means the Carry out of all 8 ALU bits is 0.

Also, the combination of the inputs forces the output of each ALU bit to follow Sum, which is forced to 1. When the F inputs are 1, this sets the 3 outputs of the "Logical unit" to 0, which means Output follows Sum and Sum is controlled by the XOR gate. Since Carry in is always 0, the output of the other XOR gate in "Full adder" is 1. Therefore, Sum is 1.