I got my hands on this ARM Artisan memory compiler for generating SRAMs. I generated .v and .lib files from it to carry out RTL simulations and synthesis. But, I have been finding it difficult to even do basic read and write operations on it. I was wondering if I could seek your help regarding the same.

For example, if I want to write to the memory, as per the documentation, SRAM requires me to have chip_enable as LOW and write_enable as active LOW as well. But, when I look at the Verilog file, there is no corresponding block that will write the memory location upon this condition being fulfilled.

Instead, the .v file does have some tasks like loadmem, dumpmem, etc. I am wondering if that is the way to go if I want to read and write to/from memory.

It's my first time using SRAM Compiler, so I am not sure if SRAM Compilers are supposed to spit out .v files in such a format.

I am happy to provide more details, if required.


1 Answer 1


Yes, memory compilers generate Verilog models (.v files) to allow you to run Verilog simulations. Simulations help you check connections to other logic and timing correctness:

  • Driving model inputs
  • Sampling model outputs

You place an instance of the memory module inside another module. For example, if your memory is controlled by controller logic that you have designed, the memory model will be an instance of a top-level module.

You can also simulate the memory model on its own if you create your own Verilog testbench. You would drive the input signals of the model (like chip_enable and write_enable). Here is an example testbench sequence:

  • At time 0, assert reset, if any.
  • Drive all other input signals to their inactive states.
  • Wait for a time as specified in the memory documentation for the reset to be asserted.
  • De-assert reset.
  • Follow the timing specifications for a memory write. Drive the chip and write enables low.
  • Wait for the specified time, then drive the enables high.

Typically, a loadmem task is used to preload all addresses in the memory with some pattern. Sometimes the memory can be preloaded from a text file of your choosing. This is a simulation convenience; the load usually occurs in zero-time, instead of the time it would take to write all of the addresses sequentially.

A dumpmem task usually allows you to write the contents of the memory out to a file. These tasks are often controlled from the testbench.


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