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I have a design that makes use of some diodes. For example, see the left figure below where I connect a diode at some node to cause the voltage at that node to saturate at a voltage given by \$V_D + V_1\$. The first thing that came to mind is to connect a MOSFET in a diode-connected configuration (see right figure). However, aside from other issues, the resistance seen looking into the drain is \$r_0\$ of the MOSFET, which is very high. Diodes typically have a very small ON resistance. Is it possible to replicate a diode behavior with MOSFETs?

enter image description here

However, I only have MOSFET transistors at my disposal. Is it possible to

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  • \$\begingroup\$ I only have MOSFET transistors at my disposal N as well as P channel? Enhancement mode as well as depletion? \$\endgroup\$
    – greybeard
    Jun 6, 2023 at 10:14
  • \$\begingroup\$ I have NMOS and PMOS. Just depletion mode. \$\endgroup\$ Jun 6, 2023 at 10:25
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    \$\begingroup\$ Why can't you have a diode? If you have both N and P channel MOSFETS, the body for one of the polarities (usually P) isn't the substrate. For a P substrate, an N well with a P (source/drain) diffusion on it makes a diode. \$\endgroup\$
    – John Doty
    Jun 6, 2023 at 10:47
  • \$\begingroup\$ I only have MOSFET transistors at my disposal Not really. Look into how those transistors are implemented in the process you're using. There is plenty of parasitic structures, including lateral bipolar transistors (!). You got diodes, you just need to visualize the process and see where they "naturally" occur. You can even use low-beta bipolar transistors I'd think - they "appear" as a side-effect of using mos devices :) Also pay attention to what isolation structures are in use in the process. Ultimately, the mos devices are just features on a mask. You can make other features :) \$\endgroup\$ Jun 6, 2023 at 23:00
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    \$\begingroup\$ I have a design that makes use of some diodes. What process is this? That's perhaps the most important question. Link to the vendor and process. I bet you there is documentation for how to get diodes and plenty of other things on the process - or someone else published a paper that includes those features (usually in processes popular in academic/research settings). \$\endgroup\$ Jun 6, 2023 at 23:03

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You have four-terminal MOSFETs, right? Use the body diode explicitly:

enter image description here

Did you catch it? -- the diode is already shown! That's what the arrow means, it's the substrate-channel junction. There's already and always* a junction there, hidden away.

*Except some (most?) SOI processes.

Mind, not in a tone of voice as calling you out personally. I honestly have no idea how and why students aren't told what the symbol actually means. This is a pervasive and systematic issue and it goes well beyond this question, or any given school for that matter.

Near as I can tell, students are just told, this symbol represents this component, deal with it, don't worry about why it's drawn that way, what it means, just use it and forget about it.

And so you get even manufacturers putting anti-parallel diodes in their symbols, as if to reiterate, yes, there is in fact a diode here, watch out for it, use it. And still I've seen my fair share of schematics where still more external diodes were added to the already be-dioded MOSFET symbol -- tripling the number of PN junctions shown on the schematic!

Compounding things further: the modern convention of the bipolar-emitter-style symbol (see the OP) hides the internal structure entirely, and in my humble opinion should be stricken from the record; there is absolutely no meaning in that poor arrow. Heck, if it's a symmetrical (traditional low voltage symmetrical lateral monolithic) FET, the arrow indeed doesn't have any meaning at all; either terminal can be used as D/S interchangeably.

Worst of all, its use is rife with confusion. I've seen datasheets with both the source arrow and substrate junction shown; I've seen them used backwards, I've seen them with outboard antiparallel diodes, and I've seen those drawn backwards too!

If people were simply told what the symbol means in the first place--!

Anyway.

Nothing need be done with the gate, and it can be omitted entirely, for that matter the source or drain can be omitted entirely as only one diffusion, and the substrate, is required to make a diode. The rest can come along, and be left open or shorted together (to S), doesn't matter. Well -- maybe it matters a little, you'd want to check the models to be sure, but in terms of broad strokes, you're still getting a PN junction, whether with extra steps or not.

A "diode strapped FET" (G wired to D) does not exhibit PN junction characteristics so cannot be used in this way. Nor can any forward gate bias, which would turn it into an Rds(on) resistor in both directions. It could be strapped G-S-SS to use the body diode in the more traditional way (traditional in the sense of discrete transistors having S-SS strapped by design), but if you have freedom of S, SS and D, you might as well connect them as above. Unless there are asymmetries in the process of course, I have no idea.

There's also the option (again, give or take process) of using source/drain diffusions, and no channel/gate, or gate tied to SS, as a lateral BJT. Then B-C can be strapped, and used as a more ideal diode than otherwise (albeit not too much better, as hFE is low for such configurations). If the process has a good BJT explicitly, obviously that can be used directly.

Disclaimer: I have no idea if they actually do it this way (dimensionally and all). It's probably pretty trivial to put a PN junction (of either polarity) in a well and let that be that. But it depends on the process, and most likely the process itself already has such elements available in the library -- use those.

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Ideal diode is usually done connecting the Mosfet reversed.
Consider schematic below if the Mosfet is off all the time (V2=0V) the rectifier is working with common 0.7V drop through body diode.
Now, if you control V2 according the potentials on AC and DC side in way:

If V_AC > V_DC put V2=10V
If V_AC < V_DC put V2=0V
you are getting an almost ideal rectifier.

Simple rectifier:

schematic

There are also other approaches how to get an ideal diode (zero drop) if you care about low power signals only, not a power rectifiers and so.

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  • \$\begingroup\$ Is this useful given Just depletion mode MOSFETs? \$\endgroup\$
    – greybeard
    Jun 7, 2023 at 6:47
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... the resistance seen looking into the drain is r0 of the MOSFET, which is very high.

This would be true if there was no connection between the drain and the gate, and if a constant voltage were applied to the gate. Then the transistor would behave like a current stabilizer with a really high drain resistance when looking into the drain.

In your "diode-connected transistor" configuration there is such negative feedback that "reverses" the transistor behaviour. Now it behaves like a voltage stabilizer when looking into the drain.

So your idea is feasible.

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Increasing the W/L ratio of the MOSFET will lower the r0.

Edit: Not sure why the answer got downgraded. Here's some additional explanation. For a diode connected configuration, the effective resistance looking from the drain is 1/gm. So, if one wants to reduce r0, gm can be increased by increasing W/L.

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