# Theoretical calculation of gate delay

I am currently working on not-gate based ring oscillators and I was wondering if there was a way to theoretically calculate without having to look at the simulation graphs the rise time and fall time of a gate.

For example, if this is my gate:

simulate this circuit – Schematic created using CircuitLab

(assume that $$\k_{p2}=k_{n1}=0.0734\$$, $$\V_\text{th1}=V_\text{th2}=0.26V\$$. You can take further assumptions if needed, please specify them if taken)

How do I theoretically calculate the rise time and the fall time of my gate? It would be helpful if a numerical answer could be provided.

• You must specify the input capacitance of the NOT gate, the trace capacitance of the input trace and the output impedance of the signal source. Otherwise, the delay will be zero. For final settling the power supply impedance of VDD and VSS is also important. Commented Jun 6, 2023 at 12:32
• ok, can you assume some valid values and provide me a way to calculate the gate delay? Commented Jun 6, 2023 at 12:35
• also, assume no impedances from power sources Commented Jun 6, 2023 at 12:36
• Then the delay will be on the order of R*C. Commented Jun 6, 2023 at 12:36
• how do you obtain that particular R was what I was wondering. Commented Jun 6, 2023 at 12:37