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I would like to know if there are already ASICs/FPGAs implemented on top triple modular redundancy for fault tolerance/if they themselves implement TMR for fault correction. Any reference to research paper describing such implementation would be appreciated

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ASICs are custom, so you can do what you want. Some FPGAs and CPLDS have built in "rad-hard" (RADiation-HARDened) versions that resist the errors rather than have fault tolerance.

But most FPGAs don't have that feature. On the last space FPGAs I worked on had 3 big FPGAs (Xilinx) for redundancy. A small rad-hard Actel FPGA to perform the TMR comparison.

Xilinx does have a tool for adding TMR within certain FPGAs.

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