Input offset voltage is an inherent flaw in the op-amp's treatment of potentials at the input. It is unrelated to input bias current, which I will talk about in a moment.
If the op-amp has open loop gain \$A\$, and non-inverting and inverting input potentials of \$V_{NINV}\$ and \$V_{INV}\$ respectively, then ideally you would like to have the relationship
$$ V_{OUT} = A(V_{NINV} - V_{INV}) $$
Unfortunately, due to inevitable asymmetry in the op-amp's internal architecture, the actual relationship has a slight offset \$V_{OS}\$ in the term \$V_{NINV} - V_{INV}\$, so that when the inputs have the same potential, the output is not actually zero:
$$ V_{OUT} = A(V_{NINV} - V_{INV} + V_{OS}) $$
This offset can be modelled with a voltage source representing this "shift" in potential at one of the inputs:
simulate this circuit – Schematic created using CircuitLab
As you can see, the closed loop gain of this amplifier is \$1+\frac{R_1}{R_2}=100\$, and the output is shifted upwards in potential by \$100 \times V_{OS} = 1V\$, even though the input \$V_{IN}=0V\$. Notice how the op-amp has successfully equalised its two input potentials (as expected with negative feedback), but that "equality" is +10mV different from \$V_{IN}\$, shown on VM1.
In other words, the output is offset by an amount equal to the product of closed-loop gain and input offset voltage. After bandwidth, I would say that input offset voltage is the biggest source of grief for engineers.
Sometimes the op-amp provides a means of restoring symmetry to some extent, allowing you to manually adjust this offset until \$V_{OS} \approx 0V\$, a feature called "offset null", or "balance". If that feature isn't present, and input offset voltage is a problem (which is often the case in high gain or multi-stage DC-coupled amplifiers), you'll have to artificially introduce an offset yourself, outside the op-amp, either prior to (at the input) or following the op-amp, to compensate for \$V_{OS}\$.
Input bias current is a different phenomenon, but has similar consequences. It's not really a problem with FET input op-amps, since input current is so small, but with bipolar input op-amps, that current can be significant, and problematic. Like input offset voltage, input bias current can result in a voltage offset. Consider this system in which I model a voltage source (the signal being amplified) with impedance 10kΩ:
simulate this circuit
The op-amp draws 1μA of current (shown on AM1) from the source V1, current which must pass through the source's own impedance. That impedance of 10kΩ develops \$V = IR = 1\mu A \times 10k\Omega = 10mV\$ (shown on VM1), and causes the voltage "seen" by the op-amp to be 10mV lower than \$V_{IN}\$, at 990mV (shown by VM2).
This voltage offset is similar in effect to input offset voltage \$V_{OS}\$, but is easier to deal with. The solution is to introduce a similar offset at the other input. If we assume that the other input draws similar current (which is approximately true for most op-amps), then all we have to do is introduce a similar impedance in that path too. That impedance will also develop a similar potential difference, and both inputs will have the same offset in potential, effectively cancelling the effects of input bias current.
For your own circuit, the trick is to find out the effective source impedance of the feedback path consisting of resistors 10kΩ and 100kΩ, and then duplicate that impedance at the other op-amp input. You're probably aware that this system of resistors can be reduced to a Thevenin equivalent:
simulate this circuit
The equivalent Thevenin resistance \$R_{TH}\$ is the parallel combination of \$R_1\$ and \$R_2\$, which is:
$$ R_{TH} = \frac{R_1R_2}{R_1 + R_2} = 9.09k\Omega $$
Viewed from this perspective, it's clear that there is effectively a resistance of 9.09kΩ between the op-amp's output \$V_O\$ and its inverting input \$V_{INV}\$, and that this resistance will develop an unwanted potential difference due to bias current drawn by the op-amp's inverting input.
To duplicate the same offset at the other input \$V_{NINV}\$, all you need is a resistance of 9.09kΩ in series with that input too:
simulate this circuit
You already have 600Ω in place, so \$R\$ will have to combine with those 600Ω to total 9.09kΩ