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I'm currently working on SDRAM in general and the IS42S16320D in particular.

My understandings until now:

  • Before reading or writing to another row you have to precharge row A and activate row B
  • You don't have to do that if you stay on the same row - you only have to give the next col/bank address
  • Using burst you can read or write multiple consecutive columns without providing a new address - and of course no precharge/activate

What I don't understand with that:
It seems that the timing when using a burst and writing or reading to the same row with manually providing the col/bank address is pretty much the same.
Am I missing something here? What's the advantage of using a burst over manually providing the addresses and checking if a row change is needed?

If it makes any difference: I'm working on a FPGA (using the DE10-lite evaboard)

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If your data size always needs BL > 1 (say you always use BL=4), then it's better for you to use the burst mode instead of issuing COL command 4 times. This is because you sometimes need to issue ACT and PRE commands (more often when your access is more like random access rather than page mode access).

If you use the BL=4, then you need to issue one column command per 4 bursts and you still have three cycle slots that you could issue row commands (ACT and PRE).

But, if you use BL=1 then you need to issue four column commands per 4 burst, so if you want to issue a row commands (to other banks), then you'll have to wait until there's a free command slot, which can impact the overall performance.

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