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In some control systems that my be composed of cascaded control loops, the reference signal of an inner loop may come from the output of the outer loop. Example in DC motor control, we have an inner current loop controlled with a PI controller, that we have an outer speed loop cascaded to the current loop.

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The reference of the inner current loop comes from the output of the speed loop. Here I have some questions:

  • The reference current here is the output of the speed controller and I know that the bandwidth of the inner loop is wider of that of the outer loop (Let's say by 10 times or higher), But I expect this reference to fluctuate a little bit (in order of millivolts) and will not be stable as manufactured voltage references like TL431. So what considerations should a designer take to connect the output of the speed controller to the input of current controller?
  • Could someone give me description or a circuit how cascaded loops are interconnected?
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  • \$\begingroup\$ You have made massive wholesale changes to your question and I for one object to this. This isn't a forum; you set your questions out and you receive answers but, you should not, having received an answer make these massive changes. I'm rolling back your question to how it was previously. You can always ask a new question formally. And, you should probably recognize that the more questions you ask, the harder it is for one person to make a full answer and, the lower the chances of getting any answers. \$\endgroup\$
    – Andy aka
    Jun 10, 2023 at 16:51
  • \$\begingroup\$ @Andyaka, I have tried to explain more and reformulate my question, in order to get an answer, but here I find it deleted with no answer !!!! \$\endgroup\$ Jun 10, 2023 at 17:18
  • \$\begingroup\$ You haven't explained more; you tagged on an additional question (how to debug your simulated system). \$\endgroup\$
    – Andy aka
    Jun 10, 2023 at 17:36
  • \$\begingroup\$ @Andyaka I have added a question to clarify my first question, concerning the interconnection of the two loops (is it a direct connection, do I need a low pass filter...), I provided a circuit with a direct connection and the problem I got. Till now I try other configurations and I'm looking elsewher for answers !! Anyway Thanks for the endeavor! \$\endgroup\$ Jun 10, 2023 at 17:45

3 Answers 3

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I saw you were looking at my answer,

  • Could someone give me description or a circuit how cascaded loops are interconnected ?

A: You do concatenate all blocks in that answer.

  • So what considerations should a designer take to connect the output of the speed controller to the input of current controller ?

A: You do limit the the current reference value to the maximum motor current for short overloads, aka I2t limit or you just limit the current to the nominal motor current if I2t is too complex. Further, at least a low pass filter is needed.

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    \$\begingroup\$ Hmm, I wouldn't say "at least"; but there may be cases where one is desired. For example, a typical op-amp implementation has an error amplifier transfer function of say -H with respect to the inverting input, but 1+H with respect to the noninverting input: there is a feed-forward component to it, which might be undesirable to have in the output. In this case, the input can be filtered by itself (applying H or something similar), prior to the error amp, to save on phase margin that an output filter would otherwise cost. \$\endgroup\$ Jul 13, 2023 at 20:50
  • \$\begingroup\$ @TimWilliams Just a small comment: A motor drive is a electromechanical system with many self resonating frequencies, each piece is elastic, spring,...somehow it is very different than a LED diode. If notch filters are too complicated, then at least one LP, it helps avoiding resonance while keeping the loop gain enough high. \$\endgroup\$ Jul 16, 2023 at 18:36
  • \$\begingroup\$ Those are good considerations, but they would normally be put into the controller's transfer function. Oh, or maybe that's what you mean, the controller generally has an overall integral characteristic (to eliminate DC error)? \$\endgroup\$ Jul 16, 2023 at 22:55
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But I expect this reference to fluctuate a little bit (in order of millivolts) and will not be stable as manufactured voltage references like TL431. So what considerations should a designer take to connect the output of the speed controller to the input of current controller?

What does it matter that the reference might fluctuate? :)

Remember, the references here are signals: in general they are functions of time (or frequency), and are expected to vary!

The control loop's responsibility is simply to follow those signals, as accurately as the design allows.

Could someone give me description or a circuit how cascaded loops are interconnected?

Sure. I'm fond of this example I made some time ago. It's from a high-power flashlight, of discrete design; a design I've used on several converters since, as I had ordered more PCBs than needed and the design is readily adaptable.

Flashlight control schematic

Obtained from my website. Copyright Tim Williams, 2017. Shared with permission.

Function is roughly by quadrant:

  • Top-left (A1-B3): ramp oscillator and bias.
  • Top-right (B3-B4): PWM comparator and gate driver. GDRV goes to a boost converter, with ground-side input current sense resistor (thus measuring current through the switching inductor).
  • Bottom-left (C2-C3): UVLO and over-temp protection; these can be ignored in normal operation.
  • Bottom-right (C4-C6): reference and error amplifiers. IC3A: output parameter (in this case, LED current, but voltage of a regulator, or speed of a motor, would do just as well here). IC3B: current control.

The stages are simply cascaded as given in your diagram:

Control loop block diagram

Instead of \$\omega_\textrm{in}^*\$, I have VREF2 from a voltage reference and potentiometer. The feedback parameter \$\omega_\textrm{in}\$ is ILED, from a shunt resistor at the output (i.e., regulating output LED current).

The limit function is afforded by the natural operating range of IC3A, a rail-to-rail op-amp. When INSP ("current negative setpoint", equivalent to \$I^*\$) is at maximum, the R16-R22 divider matches its full-scale (3.6-4.2V) value to the corresponding ratio of IBATT (input/battery current, corresponding to \$-I\$).

Likewise, IC3B's output range is constrained; the RAMP waveform is designed to cover a large amount of the total span (about 70%), so that there is little dead zone above/below the active PWM range. Such dead zones (where the output will remain at 0 or 100% PWM, i.e. there is no change in the output despite a change in the input [within the deadzone ranges]) worsen the transient response of the system, so should be minimized. This limit function is not shown on the block diagram, perhaps because it's assumed the controller and converter are designed together, and so an additional limit function does not need to be spelled out.

Instead of "converter" and "motor", I have a PWM modulator and switching converter. Largely the same thing, really; with a small rearrangement, the same power stage would run a motor quite nicely.

The sensor blocks are simply resistors. For a motor speed control, a PMDC type tachometer would furnish a voltage output that can be dropped in with minimal changes; an optical (pulse encoder) sensor would need additional signal conditioning (F-to-V converter, perhaps?).


This analog implementation seems most applicable to the present question, but equivalent statements apply to a DSP-based system, of course.

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  • \$\begingroup\$ Thanks a lot for the circuit and explanation. But, why in the outer loop, you connected the reference voltage VREF to the non-inverting input, and yet the reference generated by this controller (IC3A), is summed to the inverting input of IC3B, wouldn't be connected to non-inverting input since it is a reference to this controller (IC3B). is it due to -180 phase brought by the IC3A OP AMP? and what about the divider R16-R22, will it play the role of a divider since the non inverting is grounded and I expecte the virtual ground to appear at the summing point of IC3B? \$\endgroup\$ Jul 19, 2023 at 6:25
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    \$\begingroup\$ @learndesign "IBATT (input/battery current, corresponding to \$−I\$)" -- the feedback is already negative due to how the power section is designed. For completeness, see (my website): seventransistorlabs.com/Images/Flashlight2Sch.png And yes, IBATT1 is a virtual ground so the two signals INSP and IBATT act "equal and opposite" -- well, not equal, but in ratio given by the resistors. Like a lever, as it were. \$\endgroup\$ Jul 19, 2023 at 14:02
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The output of the speed controller (and the current limiter) is setting an objective for the current controller in the inner loop. It is saying that you can go up to this value of current or, down to some lower value of current and, dependent on the circumstances (as processed by the outer loop), those current limits may change. And yes, they will change dynamically and the inner loop has to cope.

Could someone give me description or a circuit how cascaded loops are interconnected ?

You have an example in your own question so, maybe you need to think again about what you are asking.

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  • \$\begingroup\$ I am not talking about the limits, but the flactuations of the output of speed controller, and the cascaded to the the PI controller circuits, I will provide and example in my question \$\endgroup\$ Jun 10, 2023 at 16:33
  • \$\begingroup\$ Why not sample and hold the demand over the period that the current controller would like to see a stable input. \$\endgroup\$
    – Andy aka
    Jun 10, 2023 at 18:07

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