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I have designed a (4-layer) board with impedance requirements for PCIe v2.1 (85 Ohm differential) and USB 2.0 (90 Ohm differential).

Here is a drawing of these requirements (only top and bottom layer; internal layers are all GND):

enter image description here

For this, I got a documentation from the manufacturer and I don't really understand if it's correct or wrong (as there are vias also involved and their calculation doesn't seem including the vias):

Stackup info: enter image description here

Impedance info: enter image description here

Impedance details: enter image description here

Can you confirm their calculation is correct? It seems OK without the vias. What do you think?

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    \$\begingroup\$ Shouldn't there be some ground vias directly next to the PCIe Connector ground pads, and on the other side right next to the edge connector ground pads, so as to directly connect the ground planes to the PCIe-connector/Edge-connector ? \$\endgroup\$
    – citizen
    Jun 13, 2023 at 13:32
  • \$\begingroup\$ Also was there a reason for the discontinuity in the ground-pour on the top and bottom layers ? It seems it was done on purpose ... \$\endgroup\$
    – citizen
    Jun 13, 2023 at 13:35
  • \$\begingroup\$ It looks to me like they're suggesting different width/spacing for the differential traces. You can double check their calculations if you're uncertain, but presumably they have a reason for recommending this configuration. The vias won't have 90 ohm controlled impedance, although if you know the dimensions you can probably estimate their impedance. \$\endgroup\$ Jun 13, 2023 at 14:14
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    \$\begingroup\$ You're trying to use a ground plane to make controlled impedance traces, but you haven't connected the ground connections on the edge connector to the ground plane, so your impedance will be higher than you have speced. Even with a differential signal there is still return current on the ground plane which must be routed through the connector. \$\endgroup\$ Jun 13, 2023 at 14:16
  • \$\begingroup\$ @citizen: discontinuity is for purpose: there are GND and 3V3 planes on both sides. It's a bit hard to see though. \$\endgroup\$
    – Daniel
    Jun 13, 2023 at 15:32

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Can you confirm their calculation is correct?

Assuming they used a reputable simulation program, there's no reason to think it isn't. You could ask them what program they used.

If the answer is "Polar" then the simulation is as good as it's going to get, given the inputs that are given to the program.

One thing I'd watch for is that the simulation is set up without coplanar grounds (grounds on the same plane as the traces). But physically you have coplanar grounds that are separated from the traces by about the same distance as the other traces are. If the traces are close enough for coupling to affect the impedance, then those coplanar grounds are also.

You could ask them to re-run the simulation as CBCPW ("copper-backed coplanar waveguide"). But this wouldn't give correct results in the serpentine region where the coplanar ground isn't close to all parts of the track. However if the CBCPW calculation gives "close enough" results (still within your tolerance for characteristic impedance) then that's a good sign that the coplanar ground effect is small enough not to worry about.

If the CBCPW calculation shows a big difference from the microstrip calculation, then it's a good idea to modify the design to move the coplanar ground further away from the tracks so that the microstrip calculation will be accurate.

as there are vias also involved and their calculation doesn't seem including the vias

You aren't going to get the vias included in the calculation without moving to a full 3-D simulation tool like HFSS or Microwave Office. And most board houses won't do that for you. You'd need to either get that capability in-house or hire a consultant to do it.

If you don't want to do that, you can probably improve the design by adding ground vias near the signal vias.

You can also use some empirical ("rule-of-thumb") calculators to estimate the best antipad diameter for when the signal vias pass through the L2 and L3 ground planes (Saturn PCB has this capability).


As pointed out in comments, you also want to have connections from L2 and L3 to the ground pins of the edge connector.

In general you want to have many vias connecting the ground on different layers sprinkled throughout your board ("via stitching") to make sure that all the ground layers are really at the same potential. Keeping these stitching vias spaced by less than 1/4 or even 1/8 wavelength (for the highest frequency of interest) is a reasonable rule of thumb.

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  • \$\begingroup\$ There seem to be so many different acronyms for the same thing; I've always seen it as GCPW (grounded coplanar waveguide) or CPWG (coplanar waveguide with ground). \$\endgroup\$
    – Hearth
    Jun 13, 2023 at 14:30

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