I intend to generate 22 separate 50% duty cycle pulse or square waves. The frequencies range from about 5 Hz to 350000 Hz and are all irrational numbers, so I would like as much precision as possible.

Is there some multi-channel microcontroller setup or frequency synthesizer IC which can take crystal clock sources at commonly available frequencies and use complex phase-locked-loops (PLLs) to make a large number of arbitrary frequencies?

Another post discusses using a PIC32MX1xx or 2xx series to generate a precise frequency based on complex PLLs and it seems like it would work well. But how many PLLs can one of these microcontrollers conduct simultaneously? Ideally I would like to avoid using 22 separate microcontrollers, but I suppose I could since a PIC32MX110F016B-I/SP is just $2.93. My budget is about $100.

  • 1
    \$\begingroup\$ That highly depends on the desired accuracy, resolution, and relationships (i.e. common divisors) between the individual frequencies. Some actual numbers would be nice. Also, do you need specific phase relationships between those signals? \$\endgroup\$ Jun 13 at 18:33
  • \$\begingroup\$ Look at DDS techniques. \$\endgroup\$
    – Andy aka
    Jun 13 at 18:38
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    \$\begingroup\$ @JonathanS. Exact numbers could be 8.9056 or 113119.6073 Hz. No phase relationships are required as all the frequencies are irrational. Let's assume there are no common divisors. \$\endgroup\$
    – dcsuka
    Jun 13 at 18:40
  • \$\begingroup\$ I just found the CDCE949 series of programmable clock sources, each of which has 4 separate PLLs and an adjustable load capacitor. These seem like they could work. \$\endgroup\$
    – dcsuka
    Jun 13 at 18:47
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    \$\begingroup\$ @dcsuka The difference between the 3rd and 4th convergent in this case is less than 100 parts per billion. You might find something useful in such an exploration. Just a thought. \$\endgroup\$ Jun 14 at 1:58

1 Answer 1


Not a problem. Ultimately, those "pulse" outputs are bandwidth limited, so in most general sense, for each channel you need a DAC with enough bandwidth to capture those requirements, and then the frequency generated can be arbitrary, up to the limits imposed by the SNR of the DAC.

Of course, there's a question of where you'll get a reasonably priced chip with a "bazillion" of integrated DACs and/or PLLs or FLLs that would work for your application.

I believe that either a small FPGA running at 100MHz and updating the binary outputs at that rate (10ns p-p jitter, much better long-term resolution), or a Parallax Propeller II would work.

The latter has a dedicated 8-bit DAC on every GPIO pin, and can update those DACs as fast as the cores can generate the values (update rates > 100MHz per DAC). It takes one instruction cycle to load 4 samples into a DAC.

In essence, Prop II could generate those pulse waveforms exactly to the bandwidth you need, with timing resolution likely much better than 1ns for each transition. That is generally considered a hard thing to do without fast DACs. The chip costs on the order of $20, and is dead easy to develop for - in fact, you could implement the whole thing just from the FORTH interpreter available in the boot ROM, without any PC-based dev environment if you really wanted an 80s-like workflow using a serial terminal :)

If you asked me to implement it, there'd be a table of pre-computed transition "snippets", say 8 samples long, with 100ps spacing. Assuming 100MHz DAC update rate, that's 800 samples, or about 256 32-bit HUB words to generate transitions with 100ps timing resolution.

Another approach - quite likely entirely sufficient for your needs - would be to use the high-resolution PWM frequency generators, also one per GPIO pin.

The chip has 64 GPIO pins.

Prop-II has enough "oomph" on board to serve as the transmit chain of a 100BASE-T PHY using nothing but onboard DACs, and with external ADC it can implement several full 100BASE-T PHYs in software. If you can afford the development costs for a high-volume low-cost product, it's quite a versatile part.

  • \$\begingroup\$ A 100MHz update rate means at best 10ns resolution. 100ps would need 10GHz. I suspect there are some mistakes here with SI prefixes on times, frequencies, or both. Or are you suggesting to feed the DAC output to a comparator, and managing the size of the voltage step in order to get different delays between DAC update and when the comparator switches? Perhaps combined with an analog integrator / lowpass filter, so the DAC output controls the ramp of the comparator input? \$\endgroup\$
    – Ben Voigt
    Jun 13 at 21:21
  • \$\begingroup\$ Either way, some description of the circuit between the DAC pin and the "pulse wave output" is needed. \$\endgroup\$
    – Ben Voigt
    Jun 13 at 21:22
  • \$\begingroup\$ @BenVoigt An 8-bit DAC updating at 100MHz rate can generate a bandwidth-limited square wave with a jitter below 1ns. The frequency accuracy is only limited by the width of the counter used to generate DAC values. DAC resolution affects jitter. The circuit is a single-pole roll off caused by pin capacitance and DAC source resistance - fixed in the case of Prop II. Prop II has a constant-impedance resistive output DAC with a bit of parasitic capacitance. It's inherently an RC source. Pretty neat. \$\endgroup\$ Jun 16 at 0:22

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